Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

Chihiro Tadokoro

Junichi Yamashita

Hideki Takahashi

Yoichiro Tarui

Yoshifumi Tomomatsu

Eisuke Suekawa

Kensuke Taguchi

Yasushi Takaki

Koji Okuno

Yoshihiko Hirota

Polysilicon films (P,P) are simultaneously formed on a wafer (W) and a monitor wafer (W) under the same growth condition in a wafer process. At least one of a film thickness and phosphorus concentration of the polysilicon film (P) formed on the monitor wafer (W) is measured to obtain a measured value. One of a plurality of mask patterns (A,B,C) is selected based on the measured value. The polysilicon film (P) formed on the wafer (W) is etched using the selected mask pattern to form the polysilicon resistor ().

Manufacturing method for a semiconductor device including a polysilicon resistor

A silicon carbide substrate is provided with a first surface and a second surface opposite the first surface. The silicon carbide substrate includes an n-type region connecting the first surface and the second surface, and a p-type region being in contact with the first surface and connecting the first surface and the second surface. A first anode electrode is Schottky-joined, on the first surface, to the n-type region. A first cathode electrode is ohmically joined, on the second surface, to the n-type region. A second anode electrode is ohmically joined, on the first surface, to the p-type region. A second cathode electrode is Schottky-joined, on the second surface, to the p-type region.

Silicon carbide semiconductor device having high breakdown voltage and low on resistance

A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer of a first conductivity type; a field insulating film formed on a surface of the silicon carbide semiconductor layer; a Schottky electrode formed on the surface of the silicon carbide semiconductor layer on an inner periphery side relative to the field insulating film, the Schottky electrode being formed to overlap onto the field insulating film; a front-surface electrode that covers the Schottky electrode and extends on the field insulating film beyond a peripheral edge of the Schottky electrode; and a terminal well region of a second conductivity type that is formed to be in contact with a part of the Schottky electrode in an upper part of the silicon carbide semiconductor layer and extends in the silicon carbide semiconductor layer on an outer periphery side relative to a peripheral edge of the front-surface electrode.

Silicon carbide semiconductor device

A semiconductor device includes a transistor, a first diode, and a second diode. A collector of the transistor and a cathode of the first diode are electrically connected. The collector of the transistor and a cathode of the second diode are electrically connected, and an emitter of the transistor and an anode of the second diode are electrically connected. The first diode and the second diode are formed in an identical substrate. Thereby, the semiconductor device can be produced in a smaller size and in less steps.

Semiconductor device including switching element and two diodes

A CSTBT includes a carrier stored layer () formed between a P base region () and a semiconductor substrate () and the carrier stored layer has an impurity concentration higher than that of the semiconductor substrate (). The P base region () in a periphery of a gate electrode () functions as a channel. When it is assumed that an impurity concentration of a first carrier stored layer region () just under the channel is NDand an impurity concentration of a second carrier stored layer region () other than just under the channel is NDin the carrier stored layer (), the relationship of the impurity concentrations is defined by ND&#x3c;NDThus, a gate capacity and a short-circuit current can be controlled and variation in threshold voltage can be prevented.

Insulated gate semiconductor device

An n.sup.- layer (2E) having a low impurity concentration is epitaxially grown on a surface (S1) of an n.sup.+ silicon substrate (1) having a high impurity concentration to a depth (D), and phosphorus ions (P) are implanted from the surface (S1) to the inside of the n.sup.- layer (2E). A SiO.sub.2 film is formed on the surface S1 by thermal oxidation, and an opening hole is formed in the SiO.sub.2 film. Using the opening hole, p-type impurities are implanted and diffused by thermal oxidation in the ion-implanted n.sup.- layer (2E), forming a p-type diffusion layer (well) from the surface (S1) to a predetermined depth. In this way, an n layer is formed in place of the n.sup.- layer (2E). The concentration distribution of impurity in the n layer monotonically decreases from the side of the surface (S1) and reaches its minimum on the side of an interface (BS). Then, a predetermined electrode is formed, completing the device. Thus, variations in both on-state resistance and breakdown voltage are reduced in a semiconductor device having a pn junction.

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Tokyo, Japan

Chihiro Tadokoro