Mediatek Corporation

Chihhou Tsai

Ying-Zu Lin

Chin-Yu Lin

Shan-Chih Tsou

Chao Hsin Lu

A buffer stage includes a control circuit. The control circuit includes a voltage generator, a voltage-to-current converter, and a current-to-voltage converter. The voltage generator is configured to generate a compensation voltage. The voltage-to-current converter is configured to convert the compensation voltage into a compensation current. The current-to-voltage converter is configured to convert the compensation current into a recovery compensation voltage. The recovery compensation voltage is arranged for modifying an output voltage of the buffer stage.

Buffer stage and control circuit

A reference voltage generator for an analog-to-digital converter (ADC) includes a current source coupled to a power supply, and a first transistor coupled between the current source and a first resistive circuit. The first resistive circuit is coupled to the first transistor. The reference voltage generator further includes a second transistor having a gate coupled to the current source and a gate of the first transistor, for providing a reference voltage to the ADC, an impedance circuit coupled to the second transistor, for selectively providing a variable impedance.

Reference voltage generator and analog-to-digital converter

An input buffer for an ADC is provided. The input buffer includes a receiving circuit and an impedance circuit. The receiving circuit is coupled between a power supply and a sample-and-hold circuit of the ADC, and receives an analog input signal and generating an analog signal. The impedance circuit is coupled to the receiving circuit, and selectively provides a variable impedance. When the sample-and-hold circuit of the ADC is operated in a first phase, the impedance circuit provides a small impedance, and when the sample-and-hold circuit of the ADC is operated in a second phase, the impedance circuit provides a large impedance.

Input buffer and analog-to-digital converter

A successive approximation register analog-to-digital converter (SAR ADC) with high accuracy is disclosed. Within the SAR ADC, a SAR logic circuit combines the output signal of a comparator collected during at least two successive cycles of a plurality of cycles of a search scheme of digital representation of an analog input and, accordingly, makes a one-step control for a voltage difference between a positive and a negative input terminal of the comparator. At least three capacitor network switching choices for a capacitor network of the SAR ADC are provided by the one-step control. By the one-step control, a selection between the at least three capacitor network switching choices is made according to at least two comparison results of the comparator obtained during the at least two successive cycles. In this manner, comparator noise is utilized as an additional quantization level to improve the overall ADC noise performance.

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Taipei, Taiwan

Chihhou Tsai