Changxin Memory Technologies, Inc.

ChihCheng Liu

A method for forming a capacitor opening hole and a method for forming a memory capacitor are provided. The method for forming a capacitor opening hole includes: providing a substrate, and forming a sacrificial layer and a supporting layer, which are stacked, on the surface of the substrate (S); forming multiple hollow first side wall structures, spaced apart, on the surface of the supporting layer (S); forming a second material layer on the surface of the first side wall structure to constitute a second side wall structure (S); and etching the sacrificial layer and the supporting layer by taking the first side wall structure and the second side wall structure as masks to form the capacitor opening hole (S).

Method for forming capacitor opening hole and method for forming memory capacitor

A word line structure, a manufacturing method thereof, and a semiconductor memory are provided. The word line structure includes a first word line array and a second word line array. The first word line array includes a plurality of first word lines extending in an X direction. The first word lines have a same length and are aligned and arranged in a Y direction. The second word line array includes a plurality of second word lines extending in the X direction. The second word lines have a same length and are aligned and arranged in the Y direction. The first word line array and the second word line array are not aligned in the Y direction. The Y direction is perpendicular to the X direction.

Word line structure, manufacturing method thereof and semiconductor memory

A semiconductor device and a forming method thereof are provided. The semiconductor device includes a substrate, a gate structure and a self-aligned contact structure. The substrate includes a source region and a drain region; the gate structure is formed on the substrate and are located between the source region and the drain region; and the self-aligned contact structure is formed on the substrate and includes a first contact structure, a second contact structure and a third contact structure sequentially connected in a direction perpendicular to the substrate, the first contact structure is in contact with the source region or the drain region, and a cross-sectional area of the second contact structure in a direction parallel to the substrate is greater than that of the first contact structure and that of the third contact structure in the direction parallel to the substrate.

Semiconductor device and forming method thereof

A semiconductor device includes a substrate, first word lines and second word lines; one or more first word line trenches and one or more second word line trenches are alternately arranged on the substrate in parallel; each first word line is arranged in a respective first word line trench; each second word line is arranged in a respective second word line trench, where width of the first word line trench is greater than width of the second word line trench, and depth of the first word line trench is less than depth of the second word line trench, so that width of the first word line is greater than width of the second word line, height of the first word line is less than height of the second word line, and threshold voltage of the first word line is greater than threshold voltage of the second word line.

Semiconductor device, manufacturing method of semiconductor device, and storage device

Embodiments of the present disclosure provide a forming method of a semiconductor structure and a semiconductor structure. The forming method includes: providing a base, the base includes a central region and dummy regions, and the central region includes a molding region and cutting regions; forming multiple spaced core pillars on the base; forming an initial mask layer surrounding and covering a sidewall of each core pillar on the base; removing the initial mask layers located in each cutting region to form multiple spaced mask sidewall strips in the molding region, and retaining at least one of the initial mask layers in each dummy region as a ring-shaped sidewall; removing the core pillars located in the central region and the dummy regions; and etching the base to form multiple functional structures, and etching the base to form dummy functional structures on two sides of the multiple functional structures.

Forming method of semiconductor structure and semiconductor structure

Provided is a Plasma Induced Damage (PID) test structure and a semiconductor test structure, including: a gate structure, including a gate layer; a covering dielectric layer, located on a surface of the gate layer; a metal layer structure, located on a surface of the covering dielectric layer, the metal layer structure including at least one metal layer; and an extraction electrode, electrically connected with the gate layer via a conductive structure.

PID test structure and semiconductor test structure

A bit line structure, a manufacturing method thereof, and a semiconductor memory are provided. The bit line structure includes a first bit line array and a second bit line array. The first bit line array includes a plurality of first bit lines extending in a Y direction. The plurality of first bit lines have a same length and are aligned and arranged in an X direction. The second bit line array includes a plurality of second bit lines extending in the Y direction. The plurality of second bit lines have a same length and are aligned and arranged in the X direction. The first bit line array and the second bit line array are not aligned in the X direction. The X direction is perpendicular to the Y direction.

Bit line structure, manufacturing method thereof and semiconductor memory

A die, a memory and a method of manufacturing the die are provided. The die includes a substrate and a conductive structure, where the substrate has an interconnection structure layer, the conductive structure includes a first conductive structure and a second conductive structure connected with the first conductive structure, the first conductive structure is connected with the interconnection structure layer, and a coefficient of thermal expansion of the first conductive structure is smaller than that of copper.

Die, memory and method of manufacturing die

An active region array formation method is provided, including: providing a substrate, and forming a first hard mask layer on a surface of the substrate; patterning the first hard mask layer by using a composite etching process to form an active region shielding layer in the first hard mask layer, a pattern of the active region shielding layer being matched with a pattern of a to-be-formed active region array, wherein the composite etching process includes at least two patterning processes and at least one pattern transfer process; removing the remaining first hard mask layer; and forming the active region array in the substrate through the active region shielding layer.

Active region array formation method

Disclosed are an active region, an active region array and a formation method thereof. The active region is formed in a substrate. The active region is provided with a wordline structure. The wordline structure penetrates the active region in a first direction and divides the active region into a source region and a drain region. The source region and the drain region are arranged in a second direction, and a size of the drain region in a third direction is greater than that of the source region in the third direction. An angle between the first direction and the second direction is an acute angle, and the third direction is perpendicular to the second direction.

Active region, active region array and formation method thereof

A method for forming a semiconductor structure and a semiconductor structure are provided. The method includes following operations. A semiconductor substrate is provided. The semiconductor substrate includes an array region and a peripheral region, a plurality of conductive layers are arranged in array region and separated from each other. A support layer covering the semiconductor substrate is formed. An interconnect layer is arranged in support layer located on the array region and extends to peripheral region. The interconnect layer is electrically connected to a respective one of the conductive layers and transmits an electrical signal of the respective one of the conductive layers to the peripheral region. The support layer is patterned to form a plurality of support structures located on the peripheral region and separated from each other and an interconnect structure located on the array region and peripheral region. The interconnect layer is located in the interconnect structure.

Method for forming semiconductor structure and semiconductor structure

An anti-fuse unit includes: an anti-fuse device; a first selection transistor electrically connected with the anti-fuse device; and a second selection transistor electrically connected with the first selection transistor. Each of the anti-fuse device, the first selection transistor and the second selection transistor is provided with a gate oxide layer and a gate conductive layer, the gate oxide layer of the anti-fuse device, the gate oxide layer of the first selection transistor and the gate oxide layer of the second selection transistor have a same thickness, and the gate conductive layer of the anti-fuse device, the gate conductive layer of the first selection transistor and the gate conductive layer of the second selection transistor have a same thickness.

Anti-fuse unit and anti-fuse array

The present application provides a semiconductor device, which includes a shallow trench isolation structure, located in a substrate, and comprises a first region and a second region alternately arranged. The width of the first region is greater than the width of the second region. A first filling layer and a second filling layer are sequentially arranged in the first region, and a first filling layer is arranged in the second region; wherein, in the first region, the height of the first filling layer is lower than the height of the second filling layer. The device provides an advantage that the saddle-shaped shallow trench isolation structure in the first region reduces the trapping centers during any interference from adjacent word line structures, and also reduces the overlap areas of adjacent word line structures formed subsequently, thereby reducing parasitic capacitance, curtailing leakage and improving the semiconductor device's performance.

Semiconductor device

A semiconductor device, including: a substrate; a gate oxide layer located in or on the substrate; and a gate located on a surface of the gate oxide layer, the gate including a monocrystalline silicon layer.

Semiconductor device and preparation method thereof

Embodiments provide a semiconductor device and a method of manufacturing the same. The method includes: providing a layer to be etched; forming a patterned first mask layer on the layer to be etched; and forming a patterned second mask layer formed on the layer to be etched, where the second mask layer and the first mask layer jointly define an opening, which exposes the layer to be etched; and etching the layer to be etched using the first mask layer and the second mask layer as masks, thus forming a pattern to be etched. The above-described method of manufacturing the semiconductor device allows the feature size of the first mask layer and the second mask layer to be relatively larger while keeping the device feature size the same, makes it possible to further reduce the feature size of the device.

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Hefei, China

ChihCheng Liu