Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Chiharu Ota

Johji Nishio

Takashi Shinohe

Tatsuo Shimizu

Toshihide Ito

Yukio Nakabayashi

Ryosuke Iijima

Kazuto Takao

Makoto Mizukami

Hiroshi Kono

Takuma Suzuki

Tatsunori Sakano

Tadashi Sakai

Mariko Suzuki

Susumu Obata

Tetsuo Hatakeyama

Ryosuke Iljima

Sozo Kanie

Kazuhisa Goto

According to one embodiment, a wafer includes a base body including a first surface, and a crystal layer provided on the first surface. The crystal layer includes first stacking faults and one or second stacking faults. One of the first stacking faults includes a first long side, a first short side, and a first hypotenuse. A position of the first long side in a first direction from the base body to the crystal layer is between the base body in the first direction and a first corner portion in the first direction. One of the one or the plurality of second stacking faults includes a second long side, a second short side, and a second hypotenuse. A position of a second corner portion in the first direction is between the base body in the first direction and the second long side in the first direction.

Wafer having a silicon carbide crystal layer with stacking faults provided on a silicon carbide base body and semiconductor device manufactured using the wafer

A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×10cm. Nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×10cm, and a carbon concentration at the position is equal to or less than 1×10cm.

Semiconductor device, method for manufacturing semiconductor device, inverter circuit, drive device, vehicle, and elevator

According to one embodiment, a semiconductor device includes a silicon carbide member. The silicon carbide member includes an operating region including at least one of a diode or a transistor, and a first element region including at least one element selected from the group consisting of Ar, V, Al and B. The first element region includes a first region and a second region. A first direction from the first region toward the second region is along a [1-100] direction of the silicon carbide member. The operating region is between the first region and the second region in the first direction. The first element region does not include a region overlapping the operating region in a second direction along a [11-20] direction of the silicon carbide member. Or the first element region includes a third region overlapping the operating region in the second direction.

Semiconductor device

A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×10cm. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×10cmand a carbon concentration at the first position is equal to or less than 1×10cm, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×10cm.

A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1&#xd7;10cm. Nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1&#xd7;10cm, and a carbon concentration at the position is equal to or less than 1&#xd7;10cm.

This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1&#xd7;10cm. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Zin a portion is not more than 1&#xd7;10cm. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1&#xd7;10cm, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1&#xd7;10cm.

Semiconductor device, semiconductor device manufacturing method, inverter circuit, driver device, vehicle, and elevator

A semiconductor device of embodiments includes a silicon carbide layer having a first face and a second face, a gate electrode, a gate insulating layer on the first face. The silicon carbide layer includes a first silicon carbide region of a first conductive type; a second silicon carbide region of a second conductive type disposed between the first silicon carbide region and the first face; a third silicon carbide region of a second conductive type between the first silicon carbide region and the first face; a fourth silicon carbide region; a fifth silicon carbide region; a sixth silicon carbide region of a second conductive type between the first silicon carbide region and the first face and between the second silicon carbide region and the third silicon carbide region; and a crystal defect. The crystal defect is in the sixth silicon carbide region.

A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1&#xd7;10cm. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1&#xd7;10cmand a carbon concentration at the first position is equal to or less than 1&#xd7;10cm, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1&#xd7;10cm.

According to one embodiment, a method for manufacturing a silicon carbide base body is disclosed. The method can include preparing a first base body including silicon carbide. The first base body includes a first base body surface tilted with respect to a (0001) plane of the first base body. A first line segment where the first base body surface and the (0001) plane of the first base body intersect is along a [11-20] direction of the first base body. The method can include forming a first layer at the first base body surface. The first layer includes silicon carbide. The method can include removing a portion of the first layer. The first-layer surface is tilted with respect to a (0001) plane of the first layer. A second line segment where the first-layer surface and the (0001) plane of the first layer intersect is along a [&#x2212;1100] direction.

Method for manufacturing silicon carbide base body, method for manufacturing semiconductor device, silicon carbide base body, and semiconductor device

According to one embodiment, a semiconductor device includes a silicon carbide member, first, second, and third electrodes, and a first insulating member. The silicon carbide member includes first, second, and third silicon carbide regions. The first silicon carbide region includes first, second, third, and fourth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the third partial region and the first electrode. The second silicon carbide region includes first and second semiconductor regions. The third silicon carbide region includes third and fourth semiconductor regions. The first insulating member includes first, second, and third insulating regions. The second electrode is electrically connected to the first silicon carbide region. The third and fourth partial regions are between the second and first electrodes. The third electrode is electrically connected to the second silicon carbide region.

According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include a first process of causing a stacking fault of a first semiconductor layer to expand. The first semiconductor layer includes silicon carbide and a first element and is provided on a base body including silicon carbide. The first element includes at least one selected from the group consisting of N, P, and As. The method can include a second process of forming a second semiconductor layer on the first semiconductor layer after the first process. The second semiconductor layer includes silicon carbide and the first element. The method can include a third process of forming a third semiconductor layer on the second semiconductor layer. The third semiconductor layer includes silicon carbide and a second element. The second element includes at least one selected from the group consisting of B, Al, and Ga.

Method for manufacturing semiconductor device, method for manufacturing substrate, semiconductor device, substrate, and manufacturing apparatus of substrate

According to one embodiment, a semiconductor device includes a base body including silicon carbide, a first semiconductor region including silicon carbide and a first element, and a second semiconductor region including silicon carbide and the first element. The first semiconductor region includes first and second intermediate regions. A first concentration of the first element in the first intermediate region satisfies a first or a second condition. In the first condition, the first concentration is lower than a second concentration of the first element in the second intermediate region. In the second condition, the first concentration is higher than a third concentration of a second element included in the first intermediate region, the second concentration is higher than a fourth concentration of the second element in the second intermediate region, and a difference between the first and third concentrations is smaller than a difference between the second and fourth concentrations.

Semiconductor device having a base body of silicon carbide

According to one embodiment, a semiconductor device includes first to third electrodes, first to fourth semiconductor regions, and a first insulating portion. The first semiconductor region includes first to third partial regions. The first partial region is provided between the first electrode and the second electrode. The second partial region is provided between the first and third electrodes. The second semiconductor region includes fourth to sixth partial regions. The fourth partial region is provided between the first partial region and the second electrode. The fifth partial region is provided between the third semiconductor region and at least a portion of the second partial region. The sixth partial region is provided between the third partial region and the third semiconductor region. The fourth semiconductor region is provided between the first and fourth partial regions. The first insulating portion is provided between the second partial region and the third electrode.

Growing community of inventors

Kawasaki, Japan

Chiharu Ota