Kabushiki Kaisha Toshiba

Chiharu Mizuno

Hiroshi Tanaka

Takashi Ishikawa

Kimiyoshi Usami

Mutsunori Igarashi

Masahiro Kanazawa

Sachiko Aoki

A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefor in which a first cell to which multiple supply voltages are supplied is extracted (Step S ), the extracted cells are divided into groups (Step S ), cells for voltage supply are added and arranged according to the number of the groups (Step S ), and the cell for the voltage supply are connected to the first cell for supplying the plurality of voltages through a net for a power source supply (Step S ).

SEMICONDUCTOR INTEGRATED CIRCUIT, SUPPLY METHOD FOR SUPPLYING MULTIPLE SUPPLY VOLTAGES IN SEMICONDUCTOR INTEGRATED CIRCUIT, AND RECORD MEDIUM FOR STORING PROGRAM OF SUPPLY METHOD FOR SUPPLYING MULTIPLE SUPPLY VOLTAGES IN SEMICONDUCTOR INTEGRATED CIRCUIT

A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefore in which a first cell to which multiple supply voltages are supplied is extracted (Step S1), the extracted cells are divided into groups (Step S2), cells for voltage supply are added and arranged according to the number of the groups (Step S3), and the cell for the voltage supply are connected to the first cell for supplying the plurality of voltages through a net for a power source supply (Step S4).

Semiconductor integrated circuit and supply method for supplying

A semiconductor integrated circuit capabling of reducing a chip area by facilitating optimization of a chip layout and a method for designing the same has been provided. For given gate level connection description, use cell information designating gates which should be designed by employing the cell patterns prepared in advance is generated. When the gate level connection description is developed into the transistor level, hybrid connection description including mixedly transistor level and gate level is then generated by employing the cell patterns relative to the gates which being designated by the use cell information and by developing gates which being not designated by the use cell information into transistor level. A layout is then designed based on the hybrid connection description including mixedly the transistor level and the gate level.

Growing community of inventors

Tokyo, Japan

Chiharu Mizuno