Realtek Semiconductor Inc.

National Yang Ming Chiao Tung University

Chih-Yung Shih

Liang-Wei Huang

Shieh-Hsing Kuo

Yih-Shen Chen

Chi-Shun Weng

Ray-Guang Cheng

Chung-Ju Chang

Fong-Ching Huang

An analog and digital auto-gain control method includes the steps of: providing a gain-mapping table; determining an analog gain level according to a power of a far-end transmitted signal; obtaining a gain-mapping value from the gain-mapping table according to the analog gain level; obtaining a digital gain value according to the gain-mapping value; and adjusting a gain of a digital signal according to the digital gain value. A receiver that performs the auto-gain control method is also disclosed.

Receiver and gain control method thereof

A network apparatus, for processing a network signal and outputting an output signal, includes an asynchronous signal processing module, a sampling rate converter and a synchronous signal processing module. The asynchronous signal processing module operates in an asynchronous domain, and is utilized for receiving and processing the network signal to generate a first processed signal. The sampling rate converter is coupled to the asynchronous signal processing module, and is utilized for performing sampling rate conversion on the first processed signal to generate the output signal. A first operating frequency of the asynchronous signal processing module is different from a second operating frequency of the synchronous signal processing module.

Network apparatus and network signal processing method

The present invention provides a signal processing device. The signal processing device includes a first feed forward equalizing unit, a first data slicing unit, a second feed forward equalizing unit, and a second data slicing unit. The first feed forward equalizing unit is utilized for performing a compensation operation according to a digital input signal so as to generate a first equalized signal. The first data slicing unit is coupled to the first feed forward equalizing unit, and utilized for generating a first output signal according to the first equalized signal. The second feed forward equalizing unit is coupled to the first data slicing unit, and utilized for generating a second equalized signal according to the first equalized signal. The second data slicing unit is coupled to the second feed forward equalizing unit, and utilized for generating a second output signal according to the second equalized signal.

Signal processing device having feed forward equalizing units with different tap numbers utilized in communication system

A digital slicing device is provided for making a numerical value determination with respect to an inputted modulated symbol so as to output a corresponding symbol. The digital slicing device includes a demodulating unit, a slicing unit and a re-modulating unit. The demodulating unit is for collecting at least two successive modulated symbols and for demodulating the two modulated symbols according to a modulation algorithm so as to generate two demodulated symbols. The slicing unit is for rounding the two demodulated symbols so as to generate two rounded demodulated symbols. The re-modulating unit is for re-modulating the two rounded demodulated symbols according to the modulation algorithm so as to generate two re-modulated symbols corresponding to the two modulated symbols. The two modulated symbols are generated simultaneously through conversion using the modulation algorithm.

Digital slicing device

A network apparatus for eliminating interference between transport ports includes a plurality of transport ports and at least one alien NEXT canceller. The alien NEXT canceller is coupled to a designated transport port of the plurality of transport ports for eliminating NEXT interference from other transport ports of the plurality of transport ports. The alien NEXT canceller operates in a time domain or a frequency domain. In one exemplary embodiment, the network apparatus is a switch.

Network apparatus for eliminating interference between transport ports and method thereof

A receiver for echo and crosstalk cancellation includes a level decision module, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC) and a response module. The level decision module determines plural levels and plural level magnitudes according to an estimated signal to generate a first digital signal. The DAC converts the first digital signal into a first analog signal according to the levels and the level magnitudes. The ADC receives a first difference signal between the receiving signal and the first analog signal, and converts the first difference signal into a second digital signal. According to the first digital signal, the response module generates a response signal compensating the second digital signal to generate a back-end input signal.

Receiver for echo and crosstalk cancellation and receiving method thereof

The present invention provides a signal processing device and a signal processing method utilized in a communication system, wherein the communication system includes at least a channel. The signal processing device includes an analog-to-digital converter (ADC), a first adding unit, a feed forward equalizing unit, a data slicing unit, a second adding unit, an infinite impulse response (IIR) compensating unit, and an interference eliminating unit. The signal processing device and the signal processing method thereof disclosed in the present invention can utilize the IIR compensating unit to solve an error distortion problem in the communication system so as to improve the whole efficiency.

Signal processing device and signal processing method utilized in communication system

In the implementation of timing recovery in conventional communication systems, significant errors are generated from modulo operations under certain extreme conditions by taking input signals of a slicer as datum points. In order to prevent such errors, the input signal of a modulo processing circuit is taken as the datum point in place of the input signal of a slicer. This technique could also be applied to communication systems adopting the minimum mean-square error algorithm, the zero-forcing algorithm, or other relevant algorithms.

Timing recovery circuit and method thereof

The present invention provides a network apparatus capable of canceling far-end crosstalk (FEXT). When the network apparatus is under a training mode, hard data is provided to a FEXT canceller for performing FEXT cancellation. When the network apparatus is under a data mode, soft data is provided to the FEXT canceller for performing FEXT cancellation as well. Therefore, FEXT is effectively canceled, and consumption power of the network apparatus is saved.

Network apparatus capable of canceling far-end-crosstalk and network signal processing method thereof

A digitally synchronized receiving device and an associated signal processing method are provided. The digitally synchronized receiving device can receive data transmitted by a transmitter. The transmitter and the receiving device belong to a first clock domain and a second clock domain respectively. The receiving device performs synchronization in a digital manner, so as to deal with the problem of the analog solution in prior arts and the synchronization for interference cancellation.

Digitally synchronized receiving device and associated signal processing method

A network signal processing circuit includes a first signal processing module, a first sampling rate converter, a second signal processing module, a second sampling rate converter and a timing controller. The first signal processing module is utilized for processing a network signal to output a first processed signal. The first sampling rate converter is utilized for performing signal frequency conversion on the first processed signal according to a first clock timing adjusting signal and outputting a first converted signal. The second signal processing module is utilized for processing the first converted signal to output a second processed signal. The second sampling rate converter is utilized for performing signal frequency conversion on the second processed signal according to a second clock timing adjusting signal and outputting a second converted signal. The timing controller is utilized for generating the first and second clock timing adjusting signals.

Network signal processing apparatus

A transceiver includes: a first DAC, for receiving a first digital signal to generate an analog signal; an operation circuit, coupled to the first DAC, for receiving the analog signal and a feedback signal to generate an operated analog signal; an ADC, for generating a second digital signal according to the operated analog signal; a digital signal processing circuit, for processing the second digital signal to generate a processed digital signal; a second DAC, for generating the feedback signal according to the processed digital signal; an adjustable delay circuit, for delaying a clock signal according to a control signal to adjust at least one sampling point of at least one of the first DAC, the second DAC and the ADC; and a control circuit, for generating the control signal according to the processed digital signal.

Transceiver with adjustable sampling values and signal transceiving method thereof

The present invention relates to a search circuit in a decoding unit of low-density parity-check codes, which used for searching a minimum value and a next minimum value from r input values, where r is an integer greater than 3. The search circuit includes a first search circuit and a second search circuit. The search method includes performing operations on each pair of input values Vi, Vj of the r input values, respectively. The second search circuit, which is coupled to the first search circuit, performs operations on every two sets of compared values Wm, Lm, and Wn, Ln of the s compared values, where s is a positive integer smaller than r, the smaller value Wm is smaller than the greater value Lm, and the smaller value Wn is smaller than the greater value Ln. The second search circuit performs operations according to the smaller value Wo and the greater value Lo to produce the minimum value and the next minimum value. Thereby, the search of the minimum value, the next minimum value, and the address of the minimum value can be performed at the same time without the need of waiting completion of search for the minimum value then the next minimum value can be searched.

Search circuit in decoding unit of low-density parity-check codes and method thereof

An apparatus for channel interference cancellation includes a first interference-cancellation module and a first cancellation-signal generating circuit. The first interference-cancellation module comprises a first processing circuit including a grouping circuit and a first transforming circuit. The grouping circuit divides received data into a plurality of groups of first sub-data. The first transforming circuit sequentially transforms the groups of first sub-data from a first domain to a second domain to generate a plurality of groups of first transformed sub-data. The first cancellation-signal generating circuit comprises a delay unit, a first processing unit and a second processing unit. The delay unit sequentially delays the groups of first transformed sub-data to generate a plurality of groups of delayed sub-data. The first and the second processing unit output a first and a second processed signal according to the groups of first transformed sub-data and the groups of delayed sub-data respectively.

Method and apparatus for canceling channel interference

A network apparatus with a plurality of transport ports and a shared coefficient update processor is proposed. Each of the plurality of transport ports includes a PHY module. The coefficient update processor is coupled to each PHY module and is shared by the plurality of transport ports. The coefficient update processor decides coefficients of each PHY module. The coefficient update processor is dedicated to one of the plurality of transport ports for use in a period of time.

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Taipei, Taiwan

Chih-Yung Shih