United Microelectronics Corp.

Mstar Semiconductor, Inc.

Chih-Yung Lin

Wen-Kuan Yeh

Water Lur

Juan-Yuan Wu

Tony Lin

Jiunn-Ren Hwang

Chih-Hsiang Hsiao

Chien-Wen Lai

Kevin Hsieh

Yi-Wei Wang

Cheng-Yuan Lo

Jui-Hsiang Chang

A Subscriber Identity Module (SIM) card control apparatus applied to a mobile communication device is provided. The mobile communication device has a first SIM card and a second SIM card. The SIM card control apparatus includes a judgment unit, a SIM card controller and a switch device. The judgment unit is used to generate a selection signal according to a to-be-accessed SIM card among the first and the second SIM cards. The SIM card controller transmits signals via a group of signal lines. The switch device is used to selectively connect the group of signal lines to the first SIM card or the second SIM card according to the selection signal.

Apparatus and method for controlling subscriber identity module card

A method for improving the resolution of optic lithographic is disclosed. The method includes a step of forming an etched layer on the substrate, an inorganic photoresist layer is spun-on the etched layer, and an atomic layer on the inorganic photoresist layer. Then, a deep ultraviolet light is illuminated to the inorganic photoresist layer such that the acid molecular is formed from inorganic photoresist layer. Next, the atomic layer is catalyzed by acid molecular and converted to metallic oxide by active oxygen atom. After oxidation, the oxide pattern can be obtained and it is easy by etching process.

Method for improving the resolution of optic lithography

A method of photolithography. An anti-reflective coating is formed on the conductive layer. An nitrogen plasma treatment is performed. A photo-resist layer is formed and patterned on the anti-reflective coating. The conductive layer is defined. The photo-resist layer is removed. The anti-reflective layer is removed by using phosphoric acid.

Method of photolithography

In accordance with the present invention, a method is provided for improving process window in semi-dense area by using a phase shifter. This method comprises a step of providing a transparent substrate. Then, at least two opaque regions are formed on the substrate. A phase shifter is formed in the substrate, wherein the phase shifter is formed in-between adjacent opaque regions. As a result, the phase shifter shifts the incident beam at an angle that reduces the proximity effect and improves the optical contrast and the depth of focus (DOF) to get wider process window.

Method for improving process window in semi-dense area by using phase shifter

A photolithographic process for patterning a photoresist layer over a substrate. A positive photoresist layer is formed over the substrate. The positive photoresist layer contains a photoacid generator and a photobase generator. The positive photoresist layer is exposed to light through a photomask so that the photoacid generator in the photoresist layer is changed into photoacid and the photobase generator is changed to photobase. The photomask has a first pattern region and a second pattern region that correspond with a first region and a second region of the photoresist layer. The first pattern region has a duty ratio greater than the second pattern region so that the first region is exposed to a higher light intensity than the second region. Finally, the positive photoresist layer is developed. The reaction threshold for turning the photobase generator into photobase is adjusted according to the exposure strength between the first region and the second region. Therefore, the quantity of photobase generated in the first region is much greater than in the second region. Ultimately, the diffusion of photoacid within the first region is blocked without affecting the development of the positive photoresist layer in the second region.

Photolithographic process

A copper fuse structure for integrated circuit employs two copper pads formed over a semiconductor substrate. The two copper pads are electrically insulated by dielectrics. An aluminum line is utilized to cover and electrically connect the two copper pads.

Copper fuse for integrated circuit

The invention relates to a method for adjusting a micro-bar of an electron microscope to increase the accuracy of the micro-bar. The method entails first forming a photo-resist layer on a semiconductor wafer, and exposing a predetermined region of the photo-resist layer to a light of a specific wavelength. Then, a resist stripping process is performed to remove the photo-resist layer in the predetermined region. The periphery of the predetermined region of the photo-resist layer will form a vertical side wall with a periodic wave shape similar to a sine wave, and the wavelength of the periodic wave shape is determined by the wavelength of the light and the refraction rate of the photo-resist layer. Finally, the micro-bar of the electron microscope is adjusted using the wavelength of the periodic wave shape on the vertical side wall.

Method for forming a calibation standard to adjust a micro-bar of an electron microscope

A method for forming doped p-type gate is disclosed as the following description. The method includes that, firstly, a semiconductor substrate is provided. The semiconductor substrate is etched to form a concave portion as a shallow trench isolation. A first silicon dioxide is filled into the shallow trench isolation. A n-type well is formed into the semiconductor substrate. A silicon germanium layer, named as the doped p-type layer is formed on the surface of semiconductor substrate and the surface of shallow trench isolation. A silicon nitride layer, named as the anti-reflection layer is formed on the surface of silicon germanium layer. The portions of silicon nitride layer and the portions of silicon germanium layer are etched as a gate region. The source/drain extension is formed. A second silicon dioxide layer is deposited over the surface of semiconductor substrate and the surface of nitride layer. The second silicon dioxide layer is etched as a spacer beside the sidewall of gate region. A source/drain region is formed into the semiconductor substrate. The silicon nitride layer is removed. Finally, salicide region is formed into the source/drain region and upon the surface of silcion layer to complete the silicon gate structure.

Method for forming doped p-type gate with anti-reflection layer

A method of lowering critical dimensions. A film layer and a photoresist layer are sequentially formed over a substrate. The photoresist layer is exposed and developed to form a plurality of first openings. A first baking of the photoresist layer is carried out, permitting the photoresist layer to flow. A second baking is next carried out so that the width of the first openings is reduced linearly with time until a desired dimension is reached. Using the photoresist layer as a mask, the film layer is etched to form a plurality of second openings.

Method of reducing a critical dimension of a patterned photoresist layer

A structure of combined passive elements and logic circuits on a SOI (Silicon On Insulator) wafer. By combining passive elements (including a resistor, an inductor and a capacitor) with a logic device on a SOI wafer with dual damascene technology, an extremely thick inductor that effectively reduces the resistance of the inductor can be formed while also reducing the layout area. The invention is compatible with conventional VLSI technology without increasing number of masks or process steps. Furthermore, because the resistor of the invention is composed of single crystal Si, the resistor has high stability and low noise. Therefore, the structure according to the invention is suitable for RF device design and is also suitable for a System On Chip design.

Growing community of inventors

Hsinchu Hsien, Taiwan

Chih-Yung Lin