Advanced Micro Devices Corporation

Spansion Llc.

Cypress Semiconductor Corporation

Globalfoundries Inc.

Hussmann Corporation

Monterey Research, LLC

Advanced Micro Device, Inc.

Chih-Yuh Yang

Scott Allan Bell

Cyrus E Tabery

Srikanteswara Dakshina-Murthy

Bin Yu

Minh Van Ngo

Qi Xiang

Kuo-Tung Chang

William George En

Angela Tai Hui

Shenqing Fang

Hidehiko Shiraiwa

Ning Cheng

Shibly S Ahmed

Youseok Suh

Amol Ramesh Joshi

Minghao Shen

David H Matsumoto

Lovejeet Singh

Christopher F Lyons

Ming-Ren Lin

Haihong Wang

Jeffrey Allan Shields

Hiroyuki Kinoshita

Marina V Plat

Wei Zheng

Uzodinma Okoroanyanwu

Lei Xue

Meng Ding

Chungho Lee

Tim Thurgate

Matthew S Buynoski

Arvind Halliyal

Olov B Karlsson

David Keating Foote

Philip A Fisher

Huaqiang Wu

Harpreet Kaur Sachar

Hiro Kinoshita

Fred Cheung

Ashok M Khathuria

Daniel A Steckert

Hapreet Sachar

Zoran Krivokapic

Lu You

Mark S Chang

Timothy J Thurgate

Judy Xilin An

Joong Jeon

Douglas J Bonser

Ashot Melik-Martirosian

Satoshi Torii

Allison Holbrook

Aimin Xing

Ning Cheung

Srikanteswara Dakshina-Murhty

Russell Ra Callahan

Amada Wilkison

Minh-Ren Lin

A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

System and method for manufacturing self-aligned STI with single poly

Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

Oro and orpro with bit line trench to suppress transport program disturb

Self-aligned STI with single poly for manufacturing a flash memory device

ORO and ORPRO with bit line trench to suppress transport program disturb

Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and second spacers between the bitlines, the memory device can improve the electrical isolation between the bitlines, thereby preventing and/or mitigating bitline-to-bitline current leakage and increasing BVdss.

SI trench between bitline HDP for BVDSS improvement

Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the contact hole to form the contact for the semiconductor device.

Methods for forming small contacts

Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask.

Methods for fabricating dual bit flash memory devices

Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.

Methods for fabricating flash memory devices

An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

Integrated circuit memory system employing silicon rich layers

A method of forming a fin for a fin field effect transistor (FinFET) includes defining a trench in a layer of first material, where a width of an opening of the trench is substantially smaller than a thickness of the layer. The method includes growing a second material in the trench to form the fin and removing the layer of first material.

Epitaxially grown fin for FinFET

A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.

Self aligned damascene gate

A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include depositing an organic anti-reflective coating on the gate material and forming a gate mask on the organic anti-reflective coating. The organic anti-reflective coating around the gate mask may be removed, and the gate material around the gate mask may be removed to define a gate.

Source and drain protection and stringer-free gate formation in semiconductor devices

Growing community of inventors

San Jose, CA, United States of America

Chih-Yuh Yang