United Microelectronics Corp.

Chih-Yueh Li

Bin-Siang Tsai

Fu-Yu Tsai

Kun-Ju Li

Tai-Cheng Hou

Shin-Chi Chen

Hui-Lin Wang

Chen-Yi Weng

Jing-Yin Jhang

Chun-Lung Chen

Yu-Tsung Lai

Kun-Yuan Liao

Chia-Lin Lu

Chin-Yang Hsieh

Wei-Hao Huang

Wei-Xin Gao

Chien-Hung Chen

Chun-Tsen Lu

Chau-Chung Hou

Hsin-Jung Liu

Ang Chan

Yu-Lung Shih

Chih-Jung Chen

Shui-Yen Lu

Yuan-Chi Pai

Cheng-Pu Chiu

Chi-Ying Hsieh

Shih-Min Lu

Yung-Sung Lin

Pei-Ching Yeh

Tai-Heng Yu

Fong-Lung Chuang

Tsung-Chieh Yang

Chin-Cheng Chien

Chi-Mao Hsu

Tsun-Min Cheng

Nien-Ting Ho

An-Chi Liu

Tien-Wei Yu

Chin-I Liao

Ted Ming-Lang Guo

Chih-Chung Chen

Kuan-Yu Lin

Tsung-Hsun Tsai

I-Ming Lai

Bo-Syuan Lee

Ya-Ching Cheng

Da-Ching Liao

Chun-Chi Huang

Hsin-Hsing Chen

Chih-Jen Lin

Tzu-Yi Chuang

Yung-Hung Yen

Yu-Hong Kuo

Chi-Sheng Chen

Yu-Chin Cheng

Kai-Chun Yang

Chien-Hsuan Chen

Min-Hao Yeh

Yao-Sheng Chang

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Semiconductor device and method for fabricating the same

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the second thickness is greater than the third thickness

Magnetoresistive random access memory and method for fabricating the same

A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

Magnetoresistive random access memory (MRAM) device

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Method of manufacturing magnetoresistive random access memory (MRAM) device

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.

A training apparatus and a training method for providing a sample size expanding model are provided. A normalizing unit receives a training data set with at least one numeric predictor factor and a numeric response factor. An encoding unit trains the training data set in an initial encoding layer and at least one deep encoding layer. A modeling unit extracts a mean vector and a variance vector and inputting the mean vector and the variance vector together into a latent hidden layer for obtaining the sample size expanding model. A decoding unit trains the training data set in at least one deep decoding layer and a last encoding layer. A verifying unit performs a verification of the sample size expanding model according to the outputting data set. A data generating unit generates a plurality of samples via the sample size expanding model.

Training apparatus and training method for providing sample size expanding model

A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.

FinFET with curved STI

A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.

Insulating layer next to fin structure and method of removing fin structure

A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy region defined on the substrate, and a gate electrode formed on the substrate. The dummy region is formed between the I/O region and the core region. The gate electrode crosses the I/O region and covers a portion of the dummy region.

Semiconductor structure including dummy structure and semiconductor pattern structure including dummy structure

The wafer bevel etching apparatus of the present invention includes a wafer-protecting mask to cover parts of a wafer. A central region and a wafer bevel region surrounding the central region are defined on the wafer. The wafer-protecting mask includes a center sheltering region and at least one wafer bevel sheltering region. The center sheltering region can completely shelter the central region of the wafer, and the wafer bevel sheltering region extends from the outside edge of the center sheltering region, shelters parts of the wafer bevel region, and exposes the other parts of the wafer bevel region.

Method of flattening a wafer

A semiconductor device includes an opening, a metal nitride layer, a bilayer metal layer and a conductive bulk layer. The opening is disposed in a first dielectric layer. The metal nitride layer is disposed in the opening. The bilayer metal layer is disposed on the metal nitride layer in the opening, where the bilayer metal layer includes a first metal layer and a second metal layer which is disposed on the first metal layer and has a greater metal concentration than that of the first metal layer. The conductive bulk layer is filled in the opening.

Semiconductor device having bilayer metal layer

Growing community of inventors

Taipei, Taiwan

Chih-Yueh Li