National Applied Research Laboratories

Realtek Semiconductor Inc.

Chih-Yuan Yeh

Ying-Zong Juang

Hann-Huei Tsai

Po-Chang Wu

Kuei-Cheng Lin

Yu-Chen Liu

A signal generating circuit and a signal generating method are provided. The signal generating circuit includes a first synchronization circuit configured to synchronize a beacon signal and a first signal edge of a clock signal to generate a first synchronization signal; a frequency dividing circuit configured to receive the clock signal and perform frequency division operation on the clock signal to generate a frequency division signal, wherein the duty cycle of the frequency division signal is 50%; a second synchronization circuit configured to receive the first synchronization signal and the frequency division signal and synchronize the first synchronization signal and a second signal edge of frequency division signal to generate a second synchronization signal; and a synthesis circuit configured to receive the second synchronization signal and the frequency division signal and perform AND operation on the second synchronization signal and the frequency division signal to output full-cycle signals.

Signal generating circuit and signal generating method

A signal error calibrating method is disclosed herein and includes following steps: filtering an error voltage in a sensor by a low pass filter in a calibration mode; converting the offset voltage to be a digital offset signal by an analog digital signal converter; converting the digital offset signal to be an offset calibrating signal by a digital analog signal converter; transmitting the offset calibrating signal to an input end of the sensor so as to offset an error voltage at the input end of the sensor. After calibrating the error voltage, the analog digital converter in the error calibrating circuit can be used for the need of signal output and the low pass filter is turned off at the same time.

Signal error calibrating method

A signal process circuit includes a signal modulation unit, a first resistor, a second resistor, a first discharge unit, a second discharge unit and a discharge detection unit. The signal modulation unit is used to modulate an input signal for generating a modulated signal. The first resistor is coupled between the signal modulation unit and an operation node. The second resistor is coupled between the operation node and the signal modulation unit. The first discharge unit is coupled to the signal modulation unit. The discharge unit is coupled to the signal modulation unit. The discharge detection unit is coupled to the first discharge unit, the operation node and the second discharge unit for detecting an output common voltage and control a discharge path accordingly.

Signal process circuit capable of being externally coupled to multiple types of amplifier circuits

The invention includes two parallel paths. A first path is composed of two contact ends of a first electronic switch and a first, third and fifth diodes, which connect in series. One contact end connects a first end of an AC source, and a control end connects a second end of the AC source. A second path is composed of two contact ends of a second electronic switch and a second, fourth and sixth diodes, which connect in series. One contact end connects the second end of the AC source, and a control end connects the first end of the AC source. The AC source is connected between the positive ends of the first and second diodes. The second end of the AC source separately connects negative ends of the first and third diodes through two capacitors. The first end of the AC source separately connects negative ends of the second and fourth diodes through another two capacitors. Negative ends of the fifth and sixth diodes connect together to form a voltage output end.

Master-slave voltage doubling full-wave rectifier for wireless power transfer system

A current-steering offset compensation circuit is configured for compensating an offset caused by process variation or environment variation of a signal processor. The signal processor includes a pair of differential input terminals and a pair of differential output terminals. The current-steering offset compensation circuit comprises a current-steering circuit connected with the signal processor, a digital control unit which generates a digital control signal according to the outputs from the pair of differential output terminals of the signal processor, and a digital-to-analog converter which receives the digital control signal and outputs a control voltage, wherein the current-steering circuit receives the control voltage, so as to steer the current of the pair of differential input terminals, to reduce the offset in the signal processor.

Growing community of inventors

Hsinchu, Taiwan

Chih-Yuan Yeh