Macronix International Co., Ltd.

Integrated Circuit Solution Inc.

Chih-Yuan Wu

Kuang-Wen Liu

Kai-Hsiang Chang

Ching-Chang Lin

Chun-Min Cheng

Jung-Yi Guo

Jr-Meng Wang

Chen-Chi Huang

Tsan-Lin Chen

Kuanf-Wen Liu

Shang-Pin Huang

Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. The methods may include two or more nitride removal steps during formation of gate layers in vertical memory cells. The two or more nitride removal steps may allow for wider gate layers increasing the gate fill-in, reducing the occurrence of voids, and thereby improving the word line resistance.

Methods of manufacturing semiconductor devices with improved metal gate fill-in for vertical memory cell and devices thereof

An improved semiconductor device is provided whereby the semiconductor device is defined by a layered structure comprising a first dielectric layer, a data storage material disposed on the first dielectric layer, and a second dielectric layer disposed on the data storage material, the layered structured substantially forming the outer layer of the semiconductor device. For example, the semiconductor device may be a SONOS structure having an oxide-nitride-oxide (ONO) film that substantially surrounds the SONOS structure. The invention also provides methods for fabricating the semiconductor device and the SONOS structure of the invention.

Sonos device and method for fabricating the same

A line layout method includes: forming i core layers each including a main layer that extends in a first direction and has a first end and a second end, and an end layer that is connected with the first end of the main layer and protrudes in a second direction; forming a first spacer on a sidewall of the core layer; removing the core layers; and forming 2i auxiliary patterns. i is an integer equal to or greater than 1. The auxiliary patterns extend in the first direction and are spaced and arranged in the first direction. In a region corresponding to the end layer, a portion not overlapping the auxiliary patterns has an I-beam shape.

Line layout and method of spacer self-aligned quadruple patterning for the same

An improved semiconductor device is provided whereby the semiconductor device is defined by a layered structure comprising a first dielectric layer, a data storage material disposed on the first dielectric layer, and a second dielectric layer disposed on the data storage material, the layered structured substantially forming the outer later of the semiconductor device. For example, the semiconductor device may be a SONOS structure having an oxide-nitride-oxide (ONO) film that substantially surrounds the SONOS structure. The invention also provides methods for fabricating the semiconductor device and the SONOS structure of the invention.

SONOS device and method for fabricating the same

A high access rate flash control provided for accessing more than one flash memory chip having different access timing specifications is disclosed. The controller comprises a read/write(R/W) pulse generator, a R/W delay chain circuit, a sampling delay chain circuit, a bi-directional feedback pad (PAD), a data bus sampler, and a second pad (PAD). In an embodiment, the flash controller using a fix clock to generate synchronized Read/Write pulse which is then appropriated adjusted by the R/W delay chain circuit to provide optimum R/W control signal. The adjusted R/W signal is than outputted by a bi-directional pad to flash memory chips. With the external signal feedback function, the bi-directional pad has associated with the sampling delay chain, the time latency due to pads can be eliminated nearly. Thus, the flash controller can approach high rate to access flash chips.

Growing community of inventors

Hsinchu, Taiwan

Chih-Yuan Wu