At&t Bell Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Lucent Technologies Inc.

American Telephone and Telegraph, Co.

Chih-Yuan Lu

Kuo-Hua Lee

Janmye Sung

David S Yaney

Min-Liang Chen

Steven J Hillenius

Chung W Leung

Nun-Sian Tsai

Larry B Fritzinger

Tah-Kang J Ting

Yiu M Wong

A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adjacent double or triple layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.

FET with gate spacer

A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adajcent double or triple-layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.

A compact, high speed EEPROM is disclosed. The design features mirror-image pairs of cells with a common junction buried under a thick oxide. The oxide also supports a portion of the control and floating gates. A single erase gate, also above the oxide, is capable of erasing two rows of cells at once. Each cell also has a second junction which contacts the semiconductor substrate surface. The second junction has a conductive landing pad which facilitates small cell size.

Memory device

In the manufacture of integrated-circuit semiconductor devices, prior to formation of a field oxide, a mask structure is provided on a silicon device area, comprising a pad oxide layer, a polysilicon buffer layer, a protective oxide layer, and a silicon nitride mask layer. Inclusion of the protective layer between polysilicon and silicon nitride layers prevents pad oxide failure and attendant substrate etching during strip-etching of the structure overlying the pad oxide.

Integrated-circuit device isolation

When forming a metallization layer in integrated-circuit semiconductor device fabrication, metal such as tungsten, for example, adheres poorly to a dielectric such as, e.g., silicon oxide, and tends to flake off from wafer areas not covered by a glue layer. Processing of the invention prevents such flaking by, first, removing the dielectric from the back side, edge, and 'clip-mark' areas of the wafer and, second, depositing a glue layer on remaining dielectric on the face of the wafer. Removal of dielectric material is by etching in the presence of a protective layer on the face of the wafer.

Metallization processing

A trench which provides electrical isolation between transistors on an integrated circuit substrate is described. The trench is lined with a diffusion barrier, typically a thermal oxide followed by a thermal stress relief layer, typically formed from TEOS. Then a filler material, typically BPTEOS, is deposited to fill the trench and cover the upper surface of the wafer. The filler material is heated to make it flow. Next the outer surface of the flowed filler material is next subjected to an etch-back which makes the top surface of the filled trench protrude slightly above the upper surface of the substrate. The resulting trench contains the diffusion barrier layer, the thermal stress relief layer, and the filler material. The filler material and the thermal stress relief layer will soften during subsequent heat treatments of the wafer, thus relieving thermal stresses, and preventing the occurrence of defects and dislocations within the wafer.

Semiconductor device manufacture including trench formation

Integrated circuits are fabricated with thick self-aligned silicide runners on the field oxide by etching back the first dielectric to expose patterned polysilicon on the field oxide and then forming a silicide on the patterned polysilicon.

Making silicide gate level runners

Overetching of gate runners, which may be silicided, during window etching is prevented by opening windows in the dielectric to expose the top of the silicide layer on the runners and then depositing a metal, such as tungsten, which has a high etch selectivity with respect to the dielectric. Etching can then continue to open windows which expose the source/drain regions without overetching of the gate runners because the etch used has high selectivity with respect to the dielectric and the metal.

Method for etching windows having different depths

A gate electrode having an insulating top layer as well as insulating sidewall spacers permits the source and drain regions to be electrically contacted through windows directly above the source and drain regions formed in a window pad layer. There is a conducting layer, termed a window pad layer, over portions of these regions. Because of the insulating top layer and sidewall spacers on the gate, the window may be misaligned with respect to the source and drain regions, and maybe even closer to the gate than are these regions, but electrical contacts to these regions are still obtained. The window pad layer may also be used as sublevel interconnect.

Folded extended window field effect transistor

Silicides are important for submicron VLSIC technology. Problems have been found in forming silicides by known techniques involving simply depositing a metal film and heating that metal to form a silicide layer. This invention solves the problems through recognition that polymeric contamination can be left on the surface from commonly-used previous reactive ion etch steps, and removes any such contamination to metal deposition by the additional step of heating in dry oxygen at a low temperature, such as 800 degrees Centigrade, before the contamination has been significantly hardened.

Method of making silicides by heating in oxygen to remove contamination

A gate electrode having an insulating top layer as well as insulating sidewall spacers permits the source and drain regions to be electrically contacted through windows directly above the source and drain regions formed in a window pad layer. The window pad layer may also be used as a sublevel interconnect.

Growing community of inventors

Lower Macungie Township, PA, United States of America

Chih-Yuan Lu