Industrial Technology Research Institute

Realtek Semiconductor Inc.

Chih-Yuan Cheng

Ra-Min Tain

Shyi-Ching Liau

Yung-Yu Hsu

Rong-Chang Feng

Min-Lin Lee

Chih-Kuang Yu

Chun-Kai Liu

Shou-Lung Chen

Ming-Ji Dai

Yu-Lin Chao

Shu-Jung Yang

Shan-Pu Yu

Ji-Cheng Lin

Ming-Che Hsieh

Yu-Chi Tsai

Wei Yu Li

Yi-Jen Wu

Rong-Chang Fang

Wen-tsung Huang

Yi-Hsuan Huang

A fingerprint recognition device includes a memory and a processor. The memory is configured to store at least one command. The processor is configured to read the at least one command to execute following steps: dividing a fingerprint image into a plurality of sub-areas; classifying the plurality of sub-areas into a plurality of high-quality areas and a plurality of low-quality areas according to a grayscale value ratio of the plurality of sub-areas; obtaining a first feature sample of the plurality of high-quality areas; obtaining a second feature sample of the plurality of low-quality areas, wherein a number of the first feature sample is larger than a number of the second feature sample; and outputting the first feature sample and the second feature sample.

Fingerprint recognition device and fingerprint recognition method

An active solid heatsink device and fabricating method thereof is related to a high-effective solid cooling device, where heat generated by a heat source with a small area and a high heat-generating density diffuses to a whole substrate using a heat conduction characteristic of hot electrons of a thermionic (TI) structure, and the thermionic (TI) structure and a thermo-electric (TE) structure share the substrate where the heat diffuses to. Further, the shared substrate serves as a cold end of the TE structure, and the heat diffusing to the shared substrate is pumped to another substrate of the TE structure serving as a hot end of the TE structure.

Active solid heatsink device and fabricating method thereof

An interconnect structure of an integrated circuit and manufacturing method therefore are provided, relating to an interconnect structure of flexible packaging. The interconnect structure includes a first and a second conductive pads. A plurality of tiny and conductive first pillars is respectively formed on the first and second pads. With different densities and thicknesses of the first and second pillars, a contact strength can be generated when the pillars interconnecting with each other, such that the pillars are connected closely. Furthermore, the interconnect structure can also be used to connect with fibers made of conductive materials. Moreover, the higher the density of the pillars, the stronger the contact strength. And, electronic substrates and active or passive electronic elements can be stuck on the other side of each pad. Therefore, the interconnect structure can maintain flexibility and have high reliability without being enhanced by any thermosetting polymer.

Interconnect structure of an integrated circuit and manufacturing method thereof

A chip package structure includes a substrate, a chip, a thermal conductive layer, a plurality of signal contacts, and a molding compound. The substrate includes a plurality of first thermal conductive vias, a connecting circuit, and a plurality of signal vias electrically connected to the connecting circuit, and the substrate has a chip disposing region. The chip is disposed on the chip disposing region of the substrate and electrically connected to the signal vias through the connecting circuit. The thermal conductive layer is disposed over the substrate, connected to the first thermal conductive vias, and located above the chip disposing region. Besides, the thermal conductive layer has first openings exposing the signal vias. The signal contacts are respectively disposed in the first openings and connected to the signal vias. The molding compound encapsulates the chip.

Chip package structure and manufacturing method thereof

A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.

Structure for reducing stress for vias and fabricating method thereof

Growing community of inventors

Hsinchu, Taiwan

Chih-Yuan Cheng