United Microelectronics Corp.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Yu Tseng

Kai-Ling Chiu

Victor-Chiang Liang

Cheng-Wen Fan

Kun-Szu Tseng

Victor Chiang Liang

You-Ren Liu

Chih-Chen Hsueh

Che-Hua Hsu

Chao-Sheng Cheng

Ming-Hsien Chen

Tzung-Lin Li

Chien-Ting Lin

Cheng-Chou Hung

Sheng-Yi Huang

Hui-Sheng Chang

Chia-Te Chien

Jui-Meng Jao

Yu-Jen Liu

Hsin-Kai Chiang

Chia-Pin Hung

Chin-Lan Tseng

Cheng-Hung Li

Huai-Wen Zhang

Chun-Chang Wu

Wei-Lun Hu

Disclosed is a CMOS image sensor with global shutters and a method for fabricating the CMOS image sensor. In one embodiment, a semiconductor device, includes: a light-sensing region; a charge-storage region; a light-shielding structure; and at least one via contact; wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the signal-processing region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, and wherein the light-shielding structure is simultaneously formed with the at least one via contact.

Method and apparatus for reducing light leakage at memory nodes in CMOS image sensors

A semiconductor device includes a substrate, a first metal layer, a dielectric layer, and a second metal layer. The substrate includes a dense region and an isolation region. The first metal layer is disposed over the substrate and includes a first metal pattern and a second metal pattern. The first metal pattern is located in the dense region. There is at least one slot in the first metal pattern. The second metal pattern is located in the isolation region. The dielectric layer is disposed on the first metal layer. The second metal layer is disposed on the dielectric layer.

Semiconductor device and method of fabricating the same

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a first conductive type well region in the substrate, and a second conductive type well region in the substrate. The first conductive type is different from the second conductive type. The first conductive type well region partially overlaps the second conductive type well region in an overlapping region. The semiconductor device structure also includes a source portion in the first conductive type well region and a drain portion in the second conductive type well region. The semiconductor device structure further includes a gate structure over the substrate and the overlapping region, and between the source portion and the drain portion. The semiconductor device structure further includes a first conductive type doping region in the first conductive type well region and the overlapping region.

Structure and formation method of semiconductor device structure with well regions

A semiconductor structure includes a first capacitor and a second capacitor. The first capacitor includes a plurality of first units and each first unit includes a plurality of first finger electrodes. The second capacitor includes a plurality of second units and each second unit includes a plurality of second finger electrodes. The first units and the second units are alternately arranged to form an array. The semiconductor structure further includes a plurality of first connecting lines and a plurality of second connecting lines being parallel with each other. The first connecting lines are electrically connected to the first finger electrodes, and the second connecting lines are electrically connected to the second finger electrodes. The first finger electrodes and its adjacent first connecting lines form a straight line, and the second finger electrodes and its adjacent second connecting lines form another straight line.

Semiconductor structure

The present invention provides a semiconductor structure, including a substrate, a first TSV, an inductor and a capacitor. The first TSV is disposed in the substrate and has a first signal. The inductor is disposed in the substrate. The capacitor is electrically connected to the inductor to form an LC circuit to bypass the noise from the first signal. The present invention further provides a method of reducing the signal noise in a semiconductor structure.

Semiconductor structure and method for reducing noise therein

A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.

Semiconductor device structure and fabricating method thereof

A MOS capacitor includes a substrate, a p-type MOS (pMOS) transistor positioned on the substrate, and an n-type MOS (nMOS) transistor positioned on the substrate. More important, the pMOS transistor and the nMOS transistor are electrically connected in parallel. The MOS transistor further includes a deep n-well that encompassing the pMOS transistor and the nMOS transistor.

Metal-oxide-semiconductor capacitor

A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.

Metal gate transistor with resistor

A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.

Radio frequency device and method for fabricating the same

A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.

Capacitor structure

A die seal ring disposed outside of a die region of a semiconductor substrate is disclosed. The die seal ring includes a first isolation structure, a second isolation structure, and at least one third isolation structure disposed between the first isolation structure and the second isolation structure; a plurality of first regions between the first isolation structure, the second isolation structure and the third isolation structure; a second region under the first region and the third isolation structure; and a third region under the first isolation structure.

Die seal ring

An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.

Method for fabricating metal gate transistor and polysilicon resistor

A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device.

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Hsinchu, Taiwan

Chih-Yu Tseng