Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Yu Hsu

Shih-Hao Lin

Kuo-Feng Yu

Chia-Wei Chen

Jian-Hao Chen

Shan-Mei Liao

Yen-Ming Chen

Feng-Cheng Yang

Hui-Chi Chen

Chih-Chuan Yang

Hsin-Wen Su

Kuei-Lun Lin

Yu-Chia Liang

Chia-Hao Pao

Ming-Shuan Li

Chih-Hsuan Chen

Chong-De Lien

Cheng Hong Yang

Chi On Chui

Da-Yuan Lee

Chien-Yuan Chen

Chih-Wei Lee

Cheng-Hao Hou

Tsung-Da Lin

Yao-Teng Chuang

Huang-Chin Chen

Jiao-Hao Chen

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece comprising a first channel member directly over a first region of a substrate and a second channel member directly over the first channel member, the first channel member being vertically spaced apart from the second channel member, conformally forming a dielectric layer over the workpiece, conformally depositing a dipole material layer over the dielectric layer, after the depositing of the dipole material layer, performing a thermal treatment process to the workpiece, after the performing of the thermal treatment process, selectively removing the dipole material layer, and forming a gate electrode layer over the dielectric layer.

P-type semiconductor devices with different threshold voltages and methods of forming the same

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

Post gate dielectric processing for semiconductor device fabrication

A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.

Multi-gate device and related methods

A semiconductor structure includes a first pair of source/drain features (S/D), a first stack of channel layers connected to the first pair of S/D, a second pair of S/D, and a second stack of channel layers connected to the second pair of S/D. The first pair of S/D each include a first epitaxial layer having a first dopant, a second epitaxial layer having a second dopant and disposed over the first epitaxial layer and connected to the first stack of channel layers, and a third epitaxial layer having a third dopant and disposed over the second epitaxial layer. The second pair of S/D each include a fourth epitaxial layer having a fourth dopant and connected to the second stack of channel layers, and a fifth epitaxial layer having a fifth dopant and disposed over the fourth epitaxial layer. The first dopant through the fourth dopant are of different species.

Nano-sheet-based complementary metal-oxide-semiconductor devices with asymmetric inner spacers

A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Multi-layer high-k gate dielectric structure

A semiconductor device and related method for forming a gate structure. In some embodiments, a semiconductor device includes a fin extending from a substrate. In some cases, the fin includes a plurality of semiconductor channel layers. In some examples, the semiconductor device further includes a gate dielectric surrounding each of the plurality of semiconductor channel layers. In some embodiments, a first thickness of the gate dielectric disposed on a top surface of a topmost semiconductor channel layer of the plurality of semiconductor channel layers is greater than a second thickness of the gate dielectric disposed on a surface of another semiconductor channel layer disposed beneath the topmost semiconductor channel layer.

Gate structure for multi-gate device and related methods

A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Integrated circuit device with improved reliability

A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.

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Hsinchu County, Taiwan

Chih-Yu Hsu