Vanguard International Semiconductor Corporation

Au Optronics Corporation

Wavetek Microelectronics Corporation

Realtek Semiconductor Inc.

National Applied Research Laboratories

Au Optroncis Corporation

Chih-Yen Chen

Chia-Ching Huang

Franky Juanda Lumbantoruan

Chun-Yi Wu

Shin-Cheng Lin

Han-Ping Kuo

Chang-Xiang Hung

Hsien-Lung Yang

Chih-Jen Hsiao

Tuan-Wei Wang

Chih-Wei Chen

Fu-Cheng Fan

Hsin-Chih Lin

Yen-Chung Chen

Tai-Shan Liao

Chia-Hao Wu

Wei-Chan Chang

Franco Lin

Wei-Ren Hsu

Wen-Yi Chang

Lung-Cheng Lee

Francois Hebert

Yu-Chi Sung

Zao-Shi Zheng

Shou-I Chen

Hung-Ta Hsiao

Jiunn-Jong Pan

Hsin-Chang Tsai

Chun-Yang Chen

Juin-Yang Chen

A semiconductor structure and a semiconductor device are provided. The semiconductor includes a substrate, a seed layer on the substrate, a buffer layer on the seed layer, a back barrier layer with a V-group element polarity on the buffer layer, a channel layer on the back barrier layer, and a front barrier layer on the channel layer.

Semiconductor structure and semiconductor device

A semiconductor structure includes a substrate, a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composite blocking layer. The buffer layer is on the substrate. The channel layer is on the buffer layer. The barrier layer is on the channel layer. The doped compound semiconductor layer is on the barrier layer. The composite blocking layer is on the doped compound semiconductor layer, the composite blocking layer and the barrier layer include the same Group III element, and the atomic percent of the same Group III element in the composite blocking layer increases with the distance from the doped compound semiconductor layer.

Semiconductor structure

A semiconductor structure includes a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composition gradient layer. The buffer layer is disposed on a substrate, the channel layer is disposed on the buffer layer, the barrier layer is disposed on the channel layer, the doped compound semiconductor layer is disposed on the barrier layer, and the composition gradient layer is disposed between the barrier layer and the doped compound semiconductor layer. The barrier layer and the composition gradient layer include a same group III element and a same group V element, and the atomic percentage of the same group III element in the composition gradient layer is gradually increased in the direction from the barrier layer to the doped compound semiconductor layer. A high electron mobility transistor and a fabrication method thereof are also provided.

Semiconductor structure, high electron mobility transistor and fabrication method thereof

A semiconductor structure includes a superlattice structure, an electrical isolation layer, a channel layer, and a composition gradient layer. The superlattice structure is disposed on a substrate, the electrical isolation layer is disposed on the superlattice structure, the channel layer is disposed on the electrical isolation layer, and the composition gradient layer is disposed between the electrical isolation layer and the superlattice structure. The composition gradient layer and the superlattice structure include a same group III element, and the atomic percentage of the same group III element in the composition gradient layer is gradually decreased in the direction from the superlattice structure to the electrical isolation layer. In addition, a high electron mobility transistor including the semiconductor structure is also provided.

Semiconductor structure and high electron mobility transistor

A semiconductor device is provided, including a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, an electrode structure on the epitaxial layer and an electric field modulation structure. The electrode structure includes a gate structure, a source structure and a drain structure, wherein the source structure and the drain structure are positioned on opposite sides of the gate structure. The electric field modulation structure includes an electric connection structure and a conductive layer electrically connected to the electric connection structure. The conductive layer is positioned between the gate structure and the drain structure. The electric connection structure is electrically connected to the source structure and the drain structure.

Semiconductor device

A semiconductor substrate is provided. The semiconductor substrate includes a ceramic base, a seed layer, and a nucleation layer. The ceramic base has a front surface and a back surface, and the front surface is a non-flat surface. The seed layer is disposed on the front surface of the ceramic substrate. The nucleation layer is disposed on the seed layer.

Semiconductor substrate, semiconductor device, and method for forming semiconductor structure

A memory controller includes a memory interface and a processor. The processor is coupled to the memory interface and controls access operation of a memory device via the memory interface. The processor maintains a predetermined table according to write operation of a first memory block of the memory device and performs data protection in response to the write operation. When performing the data protection, the processor determines whether memory space damage has occurred in the first memory block. When it is determined that memory space damage has occurred in the first memory block, the processor traces back one or more data sources of data written in the first memory block according to the predetermined table to obtain address information of one or more source memory blocks and performs a data recovery operation according to the address information of the one or more source memory blocks.

Data processing method and memory controller utilizing the same

A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.

Methods for forming fluorine doped high electron mobility transistor (HEMT) devices

A semiconductor device is provided. The semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a compound semiconductor layer disposed over the barrier layer, a gate electrode disposed over the compound semiconductor layer, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. The source electrode and the drain electrode penetrate through at least a portion of the barrier layer. The semiconductor device also includes a source field plate connected to the source electrode through a source contact. The semiconductor device further includes a first electric field redistribution pattern disposed on the barrier layer and directly under the edge of the source field plate.

Semiconductor devices and methods for fabricating the same

A semiconductor structure includes a seed layer on a substrate and an epitaxial stack on the seed layer. The epitaxial stack includes a first superlattice part and a second superlattice part on the first superlattice part. The first superlattice part includes first units repetitively stacked M1 times on the seed layer. Each first unit includes a first sub-layer that is an AlGaN layer, and a second sub-layer that is an AlGaN layer, wherein y1&#x3c;x1. The second superlattice part includes second units repetitively stacked M2 times on the first superlattice part. Each second unit includes a third sub-layer that is an AlGaN layer, and a fourth sub-layer that is an AlGaN layer, wherein y2&#x3c;x2. M1 and M2 are positive integers, 0&#x2264;x1, y1 and y2&#x3c;1, 0&#x3c;x2&#x2264;1, and x1&#x3c;x2, or x1=x2 and y1&#x3c;y2.

Semiconductor structure and high-electron mobility transistor device having the same

A semiconductor device is provided. The semiconductor device includes a channel layer disposed on a substrate, a barrier layer disposed on the channel layer, and a nitride layer disposed on the barrier layer. The semiconductor device also includes a compound semiconductor layer that includes an upper portion and a lower portion, wherein the lower portion penetrates through the nitride layer and a portion of the barrier layer. The semiconductor device also includes a spacer layer conformally disposed on a portion of the barrier layer and extending onto the nitride layer. The semiconductor device further includes a gate electrode disposed on the compound semiconductor layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extends through the spacer layer, the nitride layer, and at least a portion of the barrier layer.

A high electron mobility transistor includes a channel layer, a barrier layer, a first compound semiconductor layer, and a second compound semiconductor layer. The channel layer is disposed on the substrate, and the barrier layer is disposed on the channel layer. The first compound semiconductor layer is disposed on the barrier layer. The second compound semiconductor layer is disposed between the barrier layer and the first compound semiconductor layer, where the first compound semiconductor layer and the second compound semiconductor layer include a concentration distribution of metal dopant, and the concentration distribution of metal dopant includes a first peak in the first compound semiconductor layer and a second peak in the second compound semiconductor layer.

High electron mobility transistor

A package structure is provided. The package structure includes a die, a lead frame, and a conductive glue. The lead frame includes a die pad and a retaining wall structure. The die pad is configured to support the die, and the retaining wall structure surrounds the die. The conductive glue is disposed between the die and the lead frame.

Package structure

A semiconductor device includes a substrate and a first III-V compound layer disposed on the substrate. The first III-V compound layer includes a plurality of crystal lattices, each of which has a prism plane. The semiconductor device further includes a second III-V compound layer disposed on the first III-V compound layer. The semiconductor device includes a source electrode, a drain electrode and a gate electrode disposed on the second III-V compound layer. The source electrode and the drain electrode define a channel region that has a plurality of channels of charge carriers in the first III-V compound layer. The normal direction of the prism plane defines an m-axis, and each of the channels of the charge carriers is parallel with the m-axis.

Semiconductor device and manufacturing method of the same

A high-electron mobility transistor (HEMT) includes a substrate, a group III-V channel layer, a group III-V barrier layer, a group III-V cap layer, a source electrode, a first drain electrode, a second drain electrode, and a connecting portion. The group III-V channel layer, the group III-V barrier layer, and the group III-V cap layer are sequentially disposed on the substrate. The source electrode is disposed at one side of the group III-V cap layer, and the first and second drain electrodes are disposed at another side of the group III-V cap layer. The bottom surface of the first drain electrode is separated from the bottom surface of the second drain electrode, and the composition of the first drain electrode is different from the composition of the second drain electrode. The connecting portion is electrically coupled to the first drain electrode and the second drain electrode.

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Tainan, Taiwan

Chih-Yen Chen