Industrial Technology Research Institute

United Microelectronics Corp.

Kenmec Mechanical Engineering Co., Ltd.

Chih-Yao Wang

Heng-Yuan Lee

Po-Chun Yeh

Heng-Chieh Chien

Shu-Jung Yang

Yu-De Lin

Hsin-Yun Yang

Chuan-Fu Wang

Yu-Min Lin

Ping-Chia Shih

Chun-Hung Cheng

Yu-Lin Chao

Chi-Cheng Huang

Kuo-Lung Li

Shu-Hung Yu

Chih-Hao Pan

Zi-Jun Liu

Chia-Hui Huang

Wei-Yih Wu

An-Hsiu Cheng

Tien-Yuan Li

Yang-Yih Hu

Di-Kon Shih

Tao Chian

Jyi-Yu Sun

Yu-Long Lu

Kuei-Yuan Huang

A radiator and an immersion tank using the radiator is provided. The immersion tank includes a first condensation tank and the radiator. Multiple motherboards and a first working fluid are located in the first condensation tank. The radiator includes a condensation assembly and multiple heat exchanger parts. The condensation assembly is assembled outside the first condensation tank along a first direction, wherein the condensation assembly has a second condensation tank, and the second working fluid flows through the second condensation tank. Each heat exchanger part extends along the first direction, a first end of the heat exchanger part is plugged into the first condensation tank, and a second end of each heat exchanger part is plugged into the condensation assembly.

Radiators and immersion tanks using the same

A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer. The circuit substrate is electrically connected to the second redistribution structure layer of the package assembly through the connectors.

Heterogeneous integration semiconductor package structure

A ferroelectric memory is provided. The ferroelectric memory includes a substrate, a first conductive layer disposed on the substrate, a patterned oxide layer disposed on the first conductive layer and the substrate, exposing a part of the first conductive layer, a second conductive layer disposed on the exposed first conductive layer and the patterned oxide layer, an antiferroelectric layer disposed on the exposed first conductive layer and the second conductive layer, a ferroelectric layer disposed on the second conductive layer and located on the antiferroelectric layer, a conductive oxide layer disposed between the antiferroelectric layer, and a third conductive layer disposed on the conductive oxide layer and between the ferroelectric layer.

Ferroelectric memories

A ferroelectric memory is provided. The ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, at least one ferroelectric layer disposed between the first electrode and the second electrode, and at least one antiferroelectric layer disposed between the first electrode and the second electrode, wherein the antiferroelectric layer is in contact with the ferroelectric layer.

A semiconductor memory device includes a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction. A plurality of STI structures is disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions. A selection gate line is extending along a second direction and crossing over the cell regions and the STI structures. A control gate line is adjacent to the selection gate line in parallel extending along the second direction and also crosses over the cell regions and the STI structures. The selection gate line and the control gate line together form a two-transistor (2T) memory cell.

Semiconductor memory device and fabrication method thereof

A heat-pipe type solar collector includes a heat absorber portion adapted to absorb solar energy to evaporate a working fluid in heat tube elements; and a heat release portion communicating with the heat absorber portion and having a body of a semi-annular or annular cross-section. In the daytime, the vaporized working fluid exchanges heat with objects adjacent to the heat release portion. At night when temperature drops, the working fluid flows to the heat absorber portion to allow the body of the heat release portion to generate a vacuum for heat insulating purposes, thereby maintaining the temperature in the water reservoir.

Integral heat-pipe type solar collector

A high-efficiency isothermal heat pipe adapted for use in electronic equipment having a plate-like body with an enclosed inner chamber which has at least a dividing wall extending in the direction from the front end to the rear end of the body, separating the inner chamber into a plurality of zones which are interconnected by channels for the passage of a saturated working fluid filled in the inner chamber under a vacuum state. The dividing wall extends from the upper wall to the lower wall of the body and is integrally formed therewith so that the heat pipe may not distort in shape during the manufacturing process or when in use. The inner walls of the body have a plurality of grooves arranged between the front end and the rear end of the body for producing capillary action to quickly distribute heat.

High-efficiency isothermal heat pipe

Growing community of inventors

Taichung, Taiwan

Chih-Yao Wang