Faraday Technology Corporation

Chih-Yang Peng

Han-Chi Liu

Peter H Chen

Kun-Cheng Wu

Jyh-Herng Wang

Jia-Jio Huang

Chia-Nan Hong

Alvin Hsin-Hung Chen

Hanping Chen

Jim Jyh-Herng Wang

A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.

Methodology and system for setup/hold time characterization of analog IP

A methodology for characterization of an IP (Intellectual Property) component is provided. Digital pins are recognized by skipping analog pins and special IO pins. First two layers of the IP component are classified in response to connection of the input pins. Partial circuits of the IP component are extracted for simulation. Three corners of IP library are generated. Therefore, input capacitance of the IP component is simulated.

Input capacitance characterization method in IP library

Growing community of inventors

Taoyuan County, Taiwan

Chih-Yang Peng