Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Wei Sung

Keng-Ying Liao

Chi-Chung Jen

Yu-Chu Lin

Su-Yu Yeh

Chia-Ming Pan

Yi-Hung Chen

Yi-Fang Yang

Chih-Yu Wu

Po-Zen Chen

Huai-jen Tung

Yen-Jou Wu

Tzu-Pin Lin

Yung-Lung Yang

Ken-Ying Liao

A semiconductor device includes a memory region including an array of memory cell devices, and a test region including a test memory cell structure. The test memory cell structure includes a first gate stack on a first raised portion of a substrate, a first polysilicon structure adjacent to the first raised portion and in a region between the first raised portion and a second raised portion of the substrate, a first spacer adjacent to the first polysilicon structure, and a second gate stack on the second raised portion, a second polysilicon structure adjacent to the second raised portion and in the region between the first raised portion and the second raised portion, and a second spacer adjacent to the second polysilicon structure. The semiconductor device includes an interlayer dielectric layer over at least a portion of the memory region and at least a portion of the test region.

Test structure for void and topography monitoring in a flash memory device

A method includes sequentially depositing a floating gate layer, a dielectric structure stack, and a control gate layer over a substrate. A first etching process is performed to pattern the control gate layer, the dielectric structure stack, and a top portion of the floating gate layer to form a control gate, a dielectric structure, and a top portion of a floating gate over a bottom portion of the floating gate layer. A sidewall of the top portion of the floating gate is concave. A first spacer structure is formed on the sidewall of the top portion of the floating gate, a sidewall of the dielectric structure, and a sidewall of the control gate. A second etching process is performed to pattern the bottom portion of the floating gate layer to form a bottom portion of the floating gate after forming the first spacer structure.

Memory device and manufacturing method thereof

A method includes depositing a gate dielectric film over a substrate. A floating gate layer and a control gate layer are deposited over the gate dielectric film. The control gate layer is patterned to form a control gate over the floating gate layer. A top portion of the floating gate layer is patterned. A spacer structure is formed on a sidewall of the control gate and over a remaining portion of the floating gate layer. The remaining portion of the floating gate layer is patterned to form a bottom portion of a floating gate. A ratio of the bottom width of the bottom portion to the middle width of the bottom portion is in a range between about 103% and about 108%. The gate dielectric film is patterned form a gate dielectric layer.

A memory device includes a floating gate, a control gate, a spacer structure, a dielectric layer, and an erase gate. The floating gate is above a substrate. The floating gate has a curved sidewall. The control gate is above the floating gate. The spacer structure is in contact with the control gate and the floating gate. The spacer structure is spaced apart from the curved sidewall of the floating gate. The dielectric layer is in contact with the spacer structure and the curved sidewall of the floating gate. The erase gate is above the dielectric layer.

A semiconductor device having a protection layer wrapping around a conductive structure is provided. The semiconductor device comprises an image sensor device layer, an interconnect layer over the image sensor device layer, a first bonding layer over the interconnect layer, a second bonding layer bonded with the first bonding layer, a substrate over the second bonding layer, and a conductive via passing through the substrate, the second bonding layer, and the first bonding layer. The conductive via comprises a protection layer and a conductive material. The protection layer is peripherally enclosed by the substrate, the second bonding layer, and the first bonding layer. The protection layer covers a sidewall cut formed at an interface of the second bonding layer and the first bonding layer. The conductive material is peripherally enclosed by the protection layer.

Semiconductor device having protection layer wrapping around conductive structure

A semiconductor device and a method for fabricating thereof are provided. In the method for fabricating the semiconductor device, at first, a first semiconductor wafer including a first oxide layer and a second semiconductor wafer including a second oxide layer are provided. Next, the second oxide layer is bonded with the first oxide layer. Then, a through via is formed to through the second oxide layer and the first oxide layer, so as to form a sidewall cut on a sidewall of the through via at an interface of the first oxide layer and the second oxide layer. Then, an ashing operation is performed on the sidewall of the through via to form a protection layer on the sidewall of the through via. After the ashing operation is performed, a conductive material is deposited on the through via.

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Kaohsiung, Taiwan

Chih-Wei Sung