Richtek Technology Corporation

Faraday Technology Corporation

Chih-Wei Mu

Yu-Jen Cheng

Ming-Shih Yu

Wei-Chung Chang

Chih-Hsien Lin

Chieh-Min Lo

Sheng-Tsung Chen

An interface control circuit complying with an interface specification includes: an interface signal transceiver circuit and a protection circuit. The interface signal transceiver circuit is coupled to a first interface connection pin and a second interface connection pin of a first interface connector circuit. The interface signal transceiver circuit is for transmitting and/or receiving an interface signal according to the interface specification. When the interface signal transceiver circuit operates under a first state, the protection circuit determines whether a foreign object exists between the first interface connection pin and the second interface connection pin according to a voltage change or a current change at the second interface connection pin. Under the first state, the interface signal transceiver circuit generates a pull-up signal and a pull-down signal which are toggled with each other at the first interface connection pin.

Interface control circuit and control method thereof

A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value.

Delay-locked loop

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Taipei, Taiwan

Chih-Wei Mu