Industrial Technology Research Institute

National Yang Ming Chiao Tung University

Other

Rixon Tech. Co., Ltd.

Chih-Wei Liu

Po-Han Huang

Chein-Wei Jen

Tay-Jyi Lin

I-Tao Liao

Kuo-Chen Shih

Hsi-Hsin Shih

Mao-Lin Hsueh

Yi-Zhen Chen

Cheng-Wei Yeh

Shih-Hao Ou

Kuo-Chiang Chang

Hsie-Chia Chang

Yu-Wen Chen

Yuan-Hua Chu

Yen-Chin Liao

Chien-Ching Lin

Chun-Ming Liu

Chan-Hao Chang

Uei-Shin Chen

Wei-Sheng Huang

Tai-Ji Lin

Tien-Wei Hsieh

Xiang-Sheng Deng

Shin-Kai Chen

Chie-Min Chao

Tsung-Yi Wu

Pi-Chen Hsiao

An-Chi Tsai

Tse-Hao Lee

Chung-Chieh Kang

Chia-Hung Shih

A peripheral wind outlets device and a matrix wind generation system is disclosed, which is disposed on a protected space, and comprises an air supply matrix and an air exhaust matrix. The air supply matrix is composed by a plurality of peripheral wind outlets devices, disposed on a top surface of the protected space. The air exhaust matrix is composed by a plurality of peripheral air exhaust devices, disposed on a bottom surface of the protected space. The peripheral wind outlets devices and the peripheral air exhaust devices are arranged facing each other, and each has an air supply device coordinate or an air exhaust device coordinate correspondingly, the peripheral wind outlets devices and the peripheral air exhaust devices receive a wind field control command from a wind field control system, the wind field control command includes at least one first range circle and selected at least one of the peripheral wind outlets devices and at least one of the peripheral air exhaust devices located within, to make air-supply wind speeds of the at least one of the peripheral wind outlets devices are different from the air-supply wind speeds of the peripheral wind outlets devices not located within the first range circle, air-exhaust wind speeds of the at least one of the peripheral air exhaust devices are different from the air-exhaust wind speeds of the peripheral air exhaust devices not located within the first range circle.

Peripheral wind outlets device and a matrix wind generation system using the same

A catalyst system includes a transition metal salt containing a halo group, an acetate group, or a combination thereof, and an organic phosphine ligand. The molar ratio of the organic phosphine ligand to the transition metal salt is greater than 0 and less than or equal to 50.

Cayalyst system

Provided is a method for processing pipelined data using a variable-latency speculating booth multiplier (VLSBM), including a first operation and a second operation. The first operation has the steps of partitioning partial products into a least significant part (LSP) and a most significant part (MSP), estimating a carry of the LSP, computing the MSP based on the estimated carry, computing the LSP independently to obtain a true carry and detecting a computation error by comparing the estimated carry with the true carry. Also, the second operation has the step of correcting the computation error based on the difference between the estimated carry and the true carry. Further, a VLSBM for processing pipelined data is also provided.

Variable-latency speculating pipelined booth multiplier with statistical carry estimation for error detection and recovery

A catalyst system and a method for manufacturing cyclic carbonate by the same are provided. The catalyst system includes a transition metal salt containing a halo group, an acetate group, or a combination thereof, and an organic phosphine ligand. The molar ratio of the organic phosphine ligand to the transition metal salt is greater than 0 and less than or equal to 50.

Cayalyst system and manufacturing method of cyclic carbonate by the same

An arithmetic module is provided, including a first adder, a first shifter coupled to the first adder, a multiplier coupled to the first shifter for receiving an external coefficient signal, a digit alignment unit coupled to the multiplier, a second adder coupled to the digit alignment unit, and a second shifter coupled to the second adder. The arithmetic module reduces the overall computation time effectively, as compared with a scalar processor, by employing a serial data connection design, and also significantly reduces power consumption of the digital signal processor by requiring fewer input and output ends than those of a multi-issue processor.

Arithmetic module, device and system

A multicore interface with dynamic task management capability and a task loading and offloading method thereof are provided. The method disposes a communication interface between a micro processor unit (MPU) and a digital signal processor (DSP) and dynamically manages tasks assigned by the MPU to the DSP. First, an idle processing unit of the DSP is searched, and then one of a plurality of threads of the task is assigned to the processing unit. Finally, the processing unit is activated to execute the thread. Accordingly, the communication efficiency of the multicore processor can be effectively increased while the hardware cost can be saved.

Multicore interface with dynamic task management capability and task loading and offloading method thereof

A structure for LED Christmas light is provided, including a light holder, being a hollow body having a separating part connected to the inner wall of the light holder to divide the hollow interior of the light holder into two cavities. Each of the two opposite sides of the inner wall of the light holder connected to the separating part forms a slot and face the surface of the separating part of the two cavities, with each having a guiding channel. Two wire sets are fixed inside the two cavities. An LED light bulb has a positive pin and a negative pin inserted inside the guiding channel, respectively, and being electrically connected to the wire sets. A light cap has a holding part passing the LED light bulb to tightly engage to the top of the light holder so as to fix the LED light bulb to the light holder.

Structure for Christmas light

A method and corresponding apparatus for compiling high-level languages into specific processor architectures are provided. In this embodiment, the specific processor is encapsulated in a virtual processor interface with simple instruction set architecture, and a compiler translates application programs into corresponding assembly codes. Further, the difficulty of the compiler design is reduced.

Method and corresponding apparatus for compiling high-level languages into specific processor architectures

A self-compensation method includes: firstly using a min-sum algorithm to derive multiple output values in order to approach a operational result of the checking side of a belief-propagation; and then checking the present iteration number of decoding based on a checking rule; and finally, if in the previous step the present iteration number is identified with a to-be-corrected state, then performing a compensation procedure on the multiple output values, wherein the compensation term is dynamically selected in accordance with an input value of the checking nodes of the belief-propagation. The invention also provides an automatic compensation apparatus, which consists of devices such as a min-sum operating unit, and a dynamic quantization control unit, etc., which can be used, while executing the invented method described above, to decode the belief-propagation algorithm.

Method and apparatus for self-compensation on belief-propagation algorithm

A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer

An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an identical memory address concurrently, the controller controls the switch device which connects the clusters and the memory banks of the memory subsystem, so that the data item is transmitted from the cluster issuing the store instruction to the cluster issuing the load instruction through the switch device, thereby achieving data exchange between the clusters. Herein, the data item is selectively stored in the memory module depending on the address. Furthermore, the data item is also transmitted between the memory and the clusters over the switch device.

Inter-cluster communication module using the memory access network

A reconfigurable radio processor comprises a task interface and an execution kernel. The processor can be applied to a platform comprising a main processor and on-chip bus, and uses a task-based interface between the main processor and the radio processor. The radio processor simplifies the designs for control system, instruction set and data path. The bus interface includes a task dispatcher. The execution kernel comprises a global control unit, at least one function unit, an operation network, and a data network. The radio processor meets the reconfigurable and scalable requirements. It allows system designers to realize many applications on an IC chip, as well as increases the add-on values for the product. It provides system designers with the possibility of replacing another main processor under a special consideration.

Architecture of reconfigurable radio processor

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Hsinchu, Taiwan

Chih-Wei Liu