Taiwan Semiconductor Manufacturing Comp. Ltd.

Quanta Computer Incorporated

Vanguard International Semiconductor Corporation

Taimide Technology Incorporation

Mediatek Corporation

Au Optronics Corporation

Delta Electronics, Inc.

Chunghwa Picture Tubes, Ltd.

Taimide Tech. Inc.

Industrial Technology Research Institute

Realtek Semiconductor Inc.

Taimide Technology Incorporated

Chih-Wei Lin

Chung-Shi Liu

Ming-Da Cheng

Ching-Hua Hsieh

Chen-Hua Douglas Yu

Meng-Tse Chen

Wei-Hung Lin

Hsiu-Jen Lin

Wen-Hsiung Lu

Kuei-Wei Huang

Hui-Min Huang

Hao-Yi Tsai

Chun-Cheng Lin

Shing-Chao Chen

Sheng-Feng Weng

Chih-Hua Chen

Sheng-Hsiang Chiu

Chao-Jung Chen

Yu-Chih Huang

Kang-Min Kuo

Chih-Lin Wang

Yu-Peng Tsai

Chih-Fan Huang

Chen-Shien Chen

Mirng-Ji Lii

Chih-Hsuan Tai

Yen-Yu Chen

Ching-Wen Hsiao

Wen-Hao Cheng

Cheng-Ting Chen

Ming-Che Ho

Tsai-Tsung Tsai

Tin-Hao Kuo

Yu-Feng Chen

Tsung-Hsien Chiang

Tzu-Sung Huang

Hsuan-Ting Kuo

Chih-Chiang Tsao

Kuo-Lung Pan

Yu-Hao Chen

Ai-Tee Ang

Yu-Jen Cheng

Chao-Wei Li

Wei-Yu Chen

Chien Ling Hwang

Yi-Wen Wu

Ming Hung Tseng

Chun-Chih Lin

Yen-Chang Hu

Yen-Liang Lin

Chen-Cheng Kuo

Yu-Chia Lai

Chih-Cherng Liao

Chi-Ming Tsai

Bor-Ping Jang

Hao-Jan Pei

Ting-Ting Kuo

Chia-Shen Cheng

Chia-Lun Chang

Yung-Cheng Chen

Chih-Hang Tung

Yu-Wei Lin

Yi-Ming Dai

Fu-Hsien Li

Kai-Fung Chang

Ying-Jui Huang

Chih-Hsiang Lee

Chung-Ren Lao

Hung-Jui Kuo

Chin-Hsiang Lin

Cheng-Yuan Tsai

Wei-Cheng Wu

Yu-Hsiang Hu

Yaw-Tzorng Tsorng

Cheng-Ta Wu

Chun Feng Chang

Yu-Nien Huang

Sheng-Yu Wu

Hao-Cheng Hou

Heng-Jen Lee

Jung-Wei Cheng

Shih-Peng Tai

Chi-Ming Yang

Heng-Hsin Liu

Hsin-Yu Pan

Nien-Hui Kung

Jian-Hong Lin

Kuo Lung Pan

Ming-Hsien Lin

I-Hsiung Huang

Maw-Zan Jau

Li-Che Chen

Wei Sen Chang

Chung-Yi Chen

Chia-Hung Huang

Ching-Wen Chen

Meng-Wei Chou

Hsin-Chieh Lin

Yen-Hsun Hsu

Chang-Chia Huang

A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Method of fabricating memory device and package structure

A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.

Semiconductor package and manufacturing method of the same

A semiconductor package includes a first redistribution circuit structure, a semiconductor die, and an electrically conductive structure. The semiconductor die is disposed over and electrically coupled to the first redistribution circuit structure. The electrically conductive structure connects a non-active side of the semiconductor die to a conductive feature of the first redistribution circuit structure, where the semiconductor die is thermally coupled to the first redistribution circuit structure through the electrically conductive structure, and the electrically conductive structure includes a structure of multi-layer with different materials.

Semiconductor package with electrically conductive structure and manufacturing method thereof

A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

Methods of manufacturing integrated fan-out packages with embedded heat dissipation structure

A pickup apparatus for separating a semiconductor package from an adhesive film includes a platform, a roller, a moving mechanism, and a collector element. The platform has a surface disposed with the adhesive film, where the adhesive film is disposed between the platform and the semiconductor package. The roller is disposed inside the platform and under the adhesive film, where the roller includes a body and a plurality of protrusions distributed over the body. The moving mechanism is connected to the roller to control a movement of the roller. The collector element is disposed over the platform and the adhesive film, where the collector element is configured to remove the semiconductor package from the adhesive film.

Pickup apparatus and method of using the same

A package includes a redistribution structure, a bridge die, conductive pillars, connectors, a first die, first solder joints, and second solder joints. The bridge die includes a substrate, a dielectric layer disposed on the substrate, and routing patterns embedded in the dielectric layer. The conductive pillars are coupled to the redistribution structure at a position that is laterally offset from the bridge die. The connectors are coupled to the bridge die and the redistribution structure, such that the bridge die is electrically coupled to the redistribution structure through at least the connectors. The first solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the bridge die. The second solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the conductive pillars.

Package and manufacturing method thereof

A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.

Staggered metal mesh on backside of device die and method forming same

A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Package structure

A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

Fingerprint sensor device and method

A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

Semiconductor package system and method

A molded semiconductor device includes a semiconductor device and a molding material encapsulating the semiconductor device, wherein an upper surface of the molding material is substantially coplanar with an upper surface of the semiconductor device and comprises a groove at least partially surrounding the upper surface of the semiconductor device.

Molded semiconductor device and manufacturing method of molded semiconductor device

A package structure includes a first redistribution layer, a semiconductor die, and through vias. The first redistribution layer includes dielectric layers, first conductive patterns, and second conductive patterns. The dielectric layers are located in a core region and a peripheral region of the first redistribution layer. The first conductive patterns are embedded in the dielectric layers in the core region, wherein the first conductive patterns are arranged in the core region with a pattern density that gradually increases or decreases from a center of the core region to a boundary of the core region. The second conductive patterns are embedded in the dielectric layers in the peripheral region. The semiconductor die is disposed on the core region over the first conductive patterns. The through vias are disposed on the peripheral region and electrically connected to the second conductive patterns.

Package structure and method of fabricating the same

A package structure including a semiconductor die, an encapsulant, a redistribution structure, and a through insulating via is provided. The first redistribution structure includes an insulating layer and a circuit layer. The semiconductor die is disposed on the first redistribution structure. The semiconductor die includes a semiconductor base, through semiconductor vias, a dielectric layer, and bonding connectors. Through semiconductor vias penetrate through the semiconductor base. The dielectric layer is disposed on a backside of the semiconductor base. The dielectric layer of the semiconductor die is bonded with the insulating layer of the first redistribution structure. The bonding connectors are embedded in the dielectric layer and connected to the through semiconductor vias. The bonding connectors of the semiconductor die are bonded with bonding pads of the circuit layer. The encapsulant is disposed on the first redistribution structure and encapsulates the semiconductor die.

Package structure and manufacturing method thereof

A package structure including a substrate, a first semiconductor element disposed on and electrically connected with the substrate, a second semiconductor element disposed on and electrically connected with the substrate and a molding layer disposed over the substrate and covering at least a top surface of the substrate. The second semiconductor element and the first semiconductor element perform different functions. The molding layer encapsulates the second semiconductor element and wraps around sidewalls of the first semiconductor element. A top surface of the molding layer is higher than a top surface of the first semiconductor element. The molding layer has an opening extending from the top surface of the molding layer to the top surface of the first semiconductor element, so that the top surface of the first semiconductor element is exposed.

A package structure includes a first redistribution circuit structure, a semiconductor die, a connecting film, and a second redistribution circuit structure. The first redistribution circuit structure includes a dielectric structure and a routing structure disposed therein, where the dielectric structure includes a trench exposing the routing structure. The semiconductor die is disposed on and electrically coupled to the first redistribution circuit structure. The connecting film is disposed in the trench and between the semiconductor die and the first redistribution circuit structure, and the semiconductor die is thermally coupled to the routing structure through the connecting film. The second redistribution circuit structure is disposed on and electrically coupled to the semiconductor die, the second redistribution circuit structure is electrically coupled to the first redistribution circuit structure, and the semiconductor die is disposed between the first redistribution circuit structure and the second redistribution circuit structure.

Growing community of inventors

Zhubei, Taiwan

Chih-Wei Lin