Taiwan Semiconductor Manufacturing Comp. Ltd.

Quanta Computer Incorporated

Vanguard International Semiconductor Corporation

Taimide Technology Incorporation

Mediatek Corporation

Au Optronics Corporation

Delta Electronics, Inc.

Chunghwa Picture Tubes, Ltd.

Taimide Tech. Inc.

Industrial Technology Research Institute

Realtek Semiconductor Inc.

Taimide Technology Incorporated

Chih-Wei Lin

Chung-Shi Liu

Ming-Da Cheng

Ching-Hua Hsieh

Chen-Hua Douglas Yu

Meng-Tse Chen

Wei-Hung Lin

Hsiu-Jen Lin

Wen-Hsiung Lu

Kuei-Wei Huang

Hui-Min Huang

Chun-Cheng Lin

Hao-Yi Tsai

Shing-Chao Chen

Chih-Hua Chen

Sheng-Feng Weng

Chao-Jung Chen

Sheng-Hsiang Chiu

Yu-Chih Huang

Kang-Min Kuo

Chih-Lin Wang

Yu-Peng Tsai

Chih-Fan Huang

Chen-Shien Chen

Mirng-Ji Lii

Chih-Hsuan Tai

Yen-Yu Chen

Ching-Wen Hsiao

Wen-Hao Cheng

Ming-Che Ho

Cheng-Ting Chen

Tsai-Tsung Tsai

Tin-Hao Kuo

Yu-Feng Chen

Kuo-Lung Pan

Ai-Tee Ang

Yu-Jen Cheng

Chien Ling Hwang

Yi-Wen Wu

Tsung-Hsien Chiang

Chun-Chih Lin

Tzu-Sung Huang

Hsuan-Ting Kuo

Yu-Hao Chen

Yen-Chang Hu

Wei-Yu Chen

Yen-Liang Lin

Chen-Cheng Kuo

Ming Hung Tseng

Yu-Chia Lai

Chih-Cherng Liao

Chi-Ming Tsai

Bor-Ping Jang

Chih-Chiang Tsao

Ting-Ting Kuo

Chao-Wei Li

Yung-Cheng Chen

Chih-Hang Tung

Yu-Wei Lin

Hao-Jan Pei

Yi-Ming Dai

Fu-Hsien Li

Chia-Lun Chang

Chia-Shen Cheng

Chih-Hsiang Lee

Chung-Ren Lao

Hung-Jui Kuo

Chin-Hsiang Lin

Cheng-Yuan Tsai

Wei-Cheng Wu

Yaw-Tzorng Tsorng

Cheng-Ta Wu

Chun Feng Chang

Yu-Nien Huang

Sheng-Yu Wu

Hao-Cheng Hou

Heng-Jen Lee

Kai-Fung Chang

Jung-Wei Cheng

Ying-Jui Huang

Shih-Peng Tai

Yu-Hsiang Hu

Chi-Ming Yang

Heng-Hsin Liu

Hsin-Yu Pan

Nien-Hui Kung

Jian-Hong Lin

Kuo Lung Pan

Ming-Hsien Lin

I-Hsiung Huang

Maw-Zan Jau

Li-Che Chen

Wei Sen Chang

Chung-Yi Chen

Chia-Hung Huang

Meng-Wei Chou

Hsin-Chieh Lin

Yen-Hsun Hsu

Ching-Wen Chen

Chang-Chia Huang

A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Package structure

A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

Fingerprint sensor device and method

A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

Semiconductor package system and method

A molded semiconductor device includes a semiconductor device and a molding material encapsulating the semiconductor device, wherein an upper surface of the molding material is substantially coplanar with an upper surface of the semiconductor device and comprises a groove at least partially surrounding the upper surface of the semiconductor device.

Molded semiconductor device and manufacturing method of molded semiconductor device

A package structure includes a first redistribution layer, a semiconductor die, and through vias. The first redistribution layer includes dielectric layers, first conductive patterns, and second conductive patterns. The dielectric layers are located in a core region and a peripheral region of the first redistribution layer. The first conductive patterns are embedded in the dielectric layers in the core region, wherein the first conductive patterns are arranged in the core region with a pattern density that gradually increases or decreases from a center of the core region to a boundary of the core region. The second conductive patterns are embedded in the dielectric layers in the peripheral region. The semiconductor die is disposed on the core region over the first conductive patterns. The through vias are disposed on the peripheral region and electrically connected to the second conductive patterns.

Package structure and method of fabricating the same

A package structure including a semiconductor die, an encapsulant, a redistribution structure, and a through insulating via is provided. The first redistribution structure includes an insulating layer and a circuit layer. The semiconductor die is disposed on the first redistribution structure. The semiconductor die includes a semiconductor base, through semiconductor vias, a dielectric layer, and bonding connectors. Through semiconductor vias penetrate through the semiconductor base. The dielectric layer is disposed on a backside of the semiconductor base. The dielectric layer of the semiconductor die is bonded with the insulating layer of the first redistribution structure. The bonding connectors are embedded in the dielectric layer and connected to the through semiconductor vias. The bonding connectors of the semiconductor die are bonded with bonding pads of the circuit layer. The encapsulant is disposed on the first redistribution structure and encapsulates the semiconductor die.

Package structure and manufacturing method thereof

A package structure including a substrate, a first semiconductor element disposed on and electrically connected with the substrate, a second semiconductor element disposed on and electrically connected with the substrate and a molding layer disposed over the substrate and covering at least a top surface of the substrate. The second semiconductor element and the first semiconductor element perform different functions. The molding layer encapsulates the second semiconductor element and wraps around sidewalls of the first semiconductor element. A top surface of the molding layer is higher than a top surface of the first semiconductor element. The molding layer has an opening extending from the top surface of the molding layer to the top surface of the first semiconductor element, so that the top surface of the first semiconductor element is exposed.

A package structure includes a first redistribution circuit structure, a semiconductor die, a connecting film, and a second redistribution circuit structure. The first redistribution circuit structure includes a dielectric structure and a routing structure disposed therein, where the dielectric structure includes a trench exposing the routing structure. The semiconductor die is disposed on and electrically coupled to the first redistribution circuit structure. The connecting film is disposed in the trench and between the semiconductor die and the first redistribution circuit structure, and the semiconductor die is thermally coupled to the routing structure through the connecting film. The second redistribution circuit structure is disposed on and electrically coupled to the semiconductor die, the second redistribution circuit structure is electrically coupled to the first redistribution circuit structure, and the semiconductor die is disposed between the first redistribution circuit structure and the second redistribution circuit structure.

A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film. The redistribution structure is electrically connected to the conductive bumps.

Semiconductor package and manufacturing method thereof

A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.

Aligning bumps in fan-out packaging process

A semiconductor package includes a first integrated circuit and a first waveguide. The first integrated circuit includes an optical coupler. The first waveguide is optically coupled to the optical coupler. In some embodiments, the first waveguide protrudes beyond the optical coupler. In some embodiments, the first waveguide is partially overlapped with the optical coupler.

Semiconductor packages

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Integrated circuit package and method

A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

Method of fabricating semiconductor structure including a barrier structure in between a plurality of surface mount components and a wafer

Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.

Three-dimensional integrated circuit structures and methods of forming the same

A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

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Zhubei, Taiwan

Chih-Wei Lin