Nan Ya Technology Corporation

Htc Corporation

Institute for Information Industry

Richwave Technology Corp.

Entire Technology Co., Ltd.

Other

Pegatron Corporation

Lite-on It Corporation

Chih-Wei Huang

Hsu-Cheng Fan

En-Jui Li

Chih-Yu Yen

Shian-Jyh Lin

Hann-Shi Tong

Ying-Zong Juang

Chao-Sung Lai

Wen-Feng Cheng

Chuan-Jane Chao

Shyh-Chyi Wong

Yan-Zuo Chen

Ja-Hao Chen

Chieh-Pin Chang

Yeong-Her Wang

Hsing-Kan Peng

Chun-Wei Wang

Shaw-Ching Chang

Ming-Wen Tsai

Yu-Chi Chung

Chung-Yuan Lee

Chi-Ho Chang

Lei Chen

Chun-Min Lee

Ping-Chang Tsao

Cheng Tsung Lin

Chih-Hao Kuo

Hung-Chun Lin

Chun-Wei Ko

Hsiao-Wei Sung

Pei-San Tsai

Yu-Kai Shen

Yin-Sung Hsu

Chien-Jung Liu

Shang-Fong Chiu

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a drain positioned in the substrate; a top dielectric layer positioned on the substrate; a cell contact structure including a cell contact bottom conductive layer positioned in the top dielectric layer and on the drain, a cell contact top conductive layer positioned in the top dielectric layer and on the cell contact bottom conductive layer, and a cell contact top sealing layer positioned in the top dielectric layer, on the cell contact bottom conductive layer, and surrounding the cell contact top conductive layer; and a first air gap positioned in the top dielectric layer and surrounding the cell contact bottom conductive layer.

Semiconductor device with air gap and method for fabricating the same

The present disclosure provides a method for preparing metal lines with a high aspect ratio including two photolithography stages. According to the design of the method of the present disclosure, first metal lines with high aspect ratio are formed in a dielectric layer, which provides a mechanical support to the first metal lines, thereby preventing the first metal lines from collapsing or deforming. Because of a significant reduction or elimination of collapse or deformation phenomenon in the semiconductor structure, a problem associated with short circuits due to direct contact between the semiconductor components is mitigated, and reliability of the semiconductor structures is enhanced. As a result, a yield of the semiconductor structure is increased.

Method for preparing fine metal lines with high aspect ratio

A method of fabricating the semiconductor device includes forming a bit line structure over a substrate, forming a spacer structure on a sidewall of the bit line structure, partially removing an upper portion of the spacer structure to form a slope on the spacer structure slanting to the bit line structure, forming a landing pad material to cover the spacer structure and contact the slope, and removing at least a portion of the landing pad material to form a landing pad against the slope.

Semiconductor device

A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.

Manufacturing method of semiconductor structure

The present disclosure provides to a method for preparing metal lines with a high aspect ratio comprising two photolithography stages. According to the design of the method of the present disclosure, first metal lines with high aspect ratio are formed in a dielectric layer, which provides a mechanical support to the first metal lines, thereby preventing the first metal lines from collapsing or deforming. Because of a significant reduction or elimination of collapse or deformation phenomenon in the semiconductor structure, a problem associated with short circuits due to direct contact between the semiconductor components can be mitigated, and reliability of the semiconductor structures can be enhanced. As a result, a yield of the semiconductor structure is increased.

Semiconductor device and method of fabricating the same

The present application discloses a method for fabricating a semiconductor device with capacitors having a shared electrode. The method includes providing a substrate, forming a first trench in the substrate, doping sidewalls and a bottom surface of the first trench to form a bottom conductive structure, forming a first insulating layer on the bottom conductive structure and in the first trench, forming a shared conductive layer on the first insulating layer, forming a second insulating layer on the shared conductive layer, forming a top conductive layer on the second insulating layer, and forming a connection structure electrically connecting the bottom conductive structure and the top conductive layer. The bottom conductive structure, the first insulating layer, and the shared conductive layer together configure a first capacitor unit. The shared conductive layer, the second insulating layer, and the top conductive layer together configure a second capacitor unit.

Method for fabricating semiconductor device with capacitors having shared electrode

The present disclosure relates to a method for preparing an electrical fuse (e-fuse) device. The method includes forming a mask layer over a semiconductor substrate, and etching the semiconductor substrate by using the mask layer as a mask to form a fuse link over a semiconductor base. The method also includes epitaxially growing a first bottom anode/cathode region and a second bottom anode/cathode region over the semiconductor base and adjacent to a bottom portion of the fuse link. The fuse link is between the first bottom anode/cathode region and the second anode/cathode region. The method further includes epitaxially growing a top anode/cathode region to replace the mask layer.

Method for preparing vertical electrical fuse device

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate, a bit line, a dielectric layer and a word line. The substrate has an active area and a trench. The bit line is on the substrate and extends along a direction. The active area includes a first portion and a second portion respectively located at two opposite sides of the bit line and spaced apart from each other along the direction. A landing area extends from the first portion of the active area to the second portion of the active area across the bit line. A dielectric layer is in the trench. The active area is surrounded by the dielectric layer. The word line is surrounded by the dielectric layer. The word line is curved and below the bit line. A portion of the word line is between first and second end portions of the landing area.

Semiconductor structure having a landing area extends from first portion to second portion of an active area across a bit-line

The present application discloses a semiconductor device with capacitors having a shared electrode and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first capacitor unit, a second capacitor unit, and a connection structure. The first capacitor unit includes a bottom conductive structure inwardly positioned in the substrate, and a shared conductive layer positioned above the bottom conductive structure with a first insulating layer interposed therebetween. The second capacitor unit includes the shared conductive layer, a top conductive layer positioned above the shared conductive layer with a second insulating layer interposed therebetween. The connection structure electrically connects the bottom conductive structure and the top conductive layer such that the first capacitor unit and the second capacitor unit are in parallel.

Semiconductor device with capacitors having shared electrode and method for fabricating the same

The application discloses a power supply circuit and a power supply device. A drain of a first N-type metal-oxide-semiconductor field-effect transistor (MOSFET) receives a first input voltage. A filter is coupled to a source of the first N-type MOSFET and is configured to output an output voltage. A non-inverting input terminal of an operational amplifier is coupled to a ground terminal through a first capacitor. A control circuit is coupled to an inverting input terminal of the operational amplifier. One terminal of a switch is coupled to a gate of the first N-type MOSFET, and the other terminal is switchably coupled to the control circuit or an output terminal of the operational amplifier, so that the gate of the first N-type MOSFET is switched to be coupled to the control circuit or the output terminal of the operational amplifier.

Power supply device

The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of creating at least one trench in a substrate; depositing a conductive material to partially fill the trench; and forming an insulative piece in the trench and extending into the conductive material.

Method of manufacturing semiconductor device having buried word line

The present application provides a memory device with air gaps for reducing capacitive coupling. The memory device includes: a substrate, a word line, a bit line, a conductive pillar, a landing pad and a storage capacitor. The substrate has an active region. The word line is formed in the substrate and intersected with the active region. The bit line extends over the substrate and electrically connected to the active region. The conductive pillar is disposed over the substrate and electrically connected to the active region. The conductive pillar and the bit line are located at opposite sides of the word line. The landing pad is disposed on and electrically connected to the conductive pillar. A sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad. The storage capacitor is disposed over and electrically connected to the landing pad.

Memory device with air gaps for reducing capacitive coupling

The present disclosure relates to an electrical fuse (e-fuse) device and a method for forming the electrical fuse device. The vertical e-fuse device includes a fuse link disposed over a semiconductor base. A material of the fuse link and a material of the semiconductor base are the same. The vertical e-fuse device also includes a first bottom anode/cathode region and a second bottom anode/cathode region disposed over the semiconductor base. A bottom portion of the fuse link is sandwiched between the first bottom anode/cathode region and the second anode/cathode region. The vertical e-fuse device further includes a top anode/cathode region disposed over the fuse link.

Vertical electrical fuse device including fuse link disposed over semiconductor base and method for forming the same

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Taoyuan, Taiwan

Chih-Wei Huang