Via Technologies, Inc.

Primax Electronics Ltd.

Chih-Wei Hu

Yung-Huei Chen

Hsiang-Chou Huang

Yung-Tai Pan

Wallace Huang

Wen-Pin Lin

Chia-Chun Lien

Shih-Hung Yu

A vehicle bracket includes a base, a connecting piece and a fixing piece. A first surface of the base is configured to face a mounting surface. The base has a set of pivoting portions and a set of abutting portions on a second surface thereof. The set of abutting portions is configured to abut against a portion of a vehicle device. A first end of the connecting piece is rotationally and pivotally connected to the set of pivoting portions, and a second end thereof has a rod portion protruding laterally from the connecting piece. The rod portion is configured to be inserted into a guide groove of the vehicle device, so that the rod portion is limited to slide in the guide groove. The fixing piece is configured to fix the set of abutting portions and the portion of the vehicle device to each other.

Vehicle bracket and vehicle device

A pipeline module circuit structure with reduced power consumption and a method for operating the pipeline module circuit structure are provided. The pipeline module circuit structure comprises a plurality of pipeline stages and a clock generator, each of the pipeline stages connected to adjacent pipeline stages through a bus. A clock controller is installed in each of the pipeline stages, so as to set the clock frequency of a preceding pipeline stage to an idle frequency or stop when a present pipeline stage starts to operate and to set the clock frequency of a next pipeline stage to an operation frequency when the present pipeline stage is about to cease, such that the power consumption of the pipeline module circuit structure is effectively reduced.

Pipeline module circuit structure with reduced power consumption and method of operating the same

Pipeline module circuit structure with reduced power consumption controlled via bi-directional clock control buses

An apparatus and method for reducing LDRQ input pin count of a low pin count (LPC) host are provided. The LPC host is series of connecting with a plurality of peripheral devices, the peripheral device having a LDRQ control device within. The LDRQ control device comprises a LDRQ to DRQ decoder, a DRQ arbiter, and a DRQ to LDRQ encoder. In the LDRQ control device, a LDRQ signal is decoded into a DRQ signal via the LDRQ to DRQ decoder and then the DRQ signal is priority arbitrated via the DRQ arbiter. Next, the arbitrated DRQ signal is transferred into a LDRQ signal via DRQ to LDRQ encoder. Following, the LDRQ signal is outputted into the next stage peripheral device or to output into a LDRQ input pin of the LPC host, so as the LPC host only need one LDRQ input pin for purposing to effectively reduce the LDRQ input pin count and lower the manufacturing cost of the LPC host.

Apparatus and method for reducing LDRQ input pin count of a low pin count host using serially coupled peripheral devices

Growing community of inventors

Taipei, Taiwan

Chih-Wei Hu