Macronix International Co., Ltd.

Episil-precision Inc.

Macronix Internationalco., Ltd.

Chih-Wei Hu

Teng-Hao Yeh

Hang-Ting Lue

Yen-Hao Shih

Yu-Wei Jiang

Kuo-Pin Chang

Chih-Chang Hsieh

Lee-Yin Lin

Jung Hsuan

Shih-Hung Chen

Guan-Ru Lee

Chieh-Fang Chen

Jia-Rong Chiou

Teng Hao Yeh

Min-Feng Hung

Feng-Nien Tsai

Lo-Yueh Lin

Jin-Ji Dai

Yi-Jen Chan

A memory device, such as a three-dimensional AND or NOR flash memory, includes a first chip and a second chip. The first chip has multiple source line switches, multiple bit line switches, multiple page buffers, and multiple sensing amplifiers. The first chip has multiple first pads. The second chip has multiple memory cells to form multiple memory cell blocks. Multiple second pads are on a first surface of the second chip to be respectively coupled to multiple local bit lines and multiple local source lines of the memory cell blocks. Each of the first pads is coupled to the corresponding second pads.

Memory device

A memory device, such as a 3D AND type flash memory, and a compensation method of data retention thereof are provided. The compensation method includes the following. A reading operation is performed on each of a plurality of programmed memory cells of the memory device. Whether a charge loss phenomenon occurs in the programmed memory cells is determined through the reading operation to set the programmed memory cells to be charge loss memory cells. A refill program operation is performed on the charge loss memory cells.

Memory device and compensation method of data retention thereof

A 3D AND flash memory device includes a gate stack structure, a channel pillar, a source pillar, a charge storage structure, a first transistor and a second transistor. The gate stack structure is located on a dielectric substrate, wherein the gate stack structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked. The channel pillar extends through the gate stack structure. The source pillar and the drain pillar are disposed in the channel pillar and electrically connected to the channel pillar. The charge storage structure is located between the plurality of gate layers and the channel pillar. The first transistor is located above the gate stack structure and electrically connected to the drain pillar. The second transistor is located above the gate stack structure and electrically connected to the source pillar.

3D and flash memory device and method of fabricating the same

A memory device, such as three dimension AND Flash memory, including a plurality of word line decoding circuit areas, a plurality of common power rails and a plurality of power drivers is provided. The word line decoding circuit areas are arranged in an array, and form a plurality of isolation areas, wherein each of the isolation areas is disposed between two adjacent word line decoding circuit areas. Each of the common power rails is disposed along the isolation areas. The power drivers respectively correspond to the word line decoding circuit areas. Each of the power drivers is disposed between each of the power driving circuit areas and each of the corresponding isolation areas, wherein each of the power drivers is configured to provide a common power to the word line decoding circuit areas.

A three-dimensional AND flash memory device includes a stack structure, isolators, channel pillars, source pillars and drain pillars, and charge storage structures. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The isolators divide the stack structure into sub-blocks and include walls and slits. The walls include isolation layers and the insulating layers stacked alternately with each other, and the isolation layers are buried in the gate layers. The slits alternate with the walls, and each of the slits extends through the stack structure. The channel pillars extend through the stack structure in each of the sub-blocks. The source pillars and the drain pillars are located in the channel pillars. The charge storage structures are located between the gate layers and the channel pillar.

3D AND flash memory device and method of fabricating the same

A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

A memory device includes a stacked structure and at least one first element structure. The stacked structure is in a memory array region and a staircase contact region. The stacked structure includes first conductive layers and a second conductive layer arranged in a longitudinal direction. The memory array region and the staircase contact region are arranged in a first lateral direction. The at least one first element structure passes through the first conductive layers and the second conductive layer along the longitudinal direction. The first conductive layers surround a sidewall surface of the at least one first element structure. The second conductive layer includes conductive portions arranged in a second lateral direction. The conductive portions are completely separated from each other by the at least one first element structure. The first lateral direction is different from the second lateral direction.

A semiconductor structure includes a stack of memory cells and a CMOS structure. The CMOS structure is located below the stack of memory cells. The CMOS structure includes a source line transistor and a bit line transistor.

Semiconductor structure

A memory device comprises a stack of patterned conductor layers, at least a plurality of the layers comprising conductive strips including strips continuous with a pad and other strips isolated from the pad. An array of vertical pillars extends through the stack of patterned conductor layers, wherein memory cells are disposed at cross-points between the vertical pillars and patterned conductor layers. The array has an array boundary proximal to the pad. A first set of isolation blocks extends through the plurality of patterned conductor layers separating the strips continuous with the pad from the other strips isolated from the pad. A second set of isolation blocks inside the array boundary extends through the plurality of patterned conductor layers isolating the other strips from the pad.

Dummy vertical structures for etching in 3D NAND memory and other circuits

A memory device and a manufacturing method for the same are provided. The memory device comprises a stack structure and a channel structure. The stack structure is on a substrate and comprises gate electrodes and insulating films stacked alternately. The channel structure is electrically coupled to the gate electrodes, and is on sidewall surfaces of the gate electrodes. The channel structure comprises a first channel structure and a second channel structure. The second channel structure is on an upper surface of the first channel structure. The first channel structure and/or the second channel structure has a ring shape.

Memory device and manufacturing method for the same

A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure. The multi-layer stacked structure includes a stair region and an non-stair region, the stair region includes a plurality of steps, each step includes an immediately-adjacent pair of the conductive layers and insulating layers. A plurality of memory structures are located in the non-stair region, and each memory structure passes through the conductive layers and the insulating layers. A fishbone dielectric structure includes a main bone and a plurality of side bones extending from the main bone in the stair region, wherein the main bone crosses the memory structures in the non-stair region.

Three dimensional memory device

A memory device and a method for manufacturing the same are provided. A memory device includes a drain pillar structure, a source pillar structure, a charge trapping structure, a vertical channel structure and a gate structure. The drain pillar structure is formed in a first opening. The source pillar structure is formed in a second opening. The vertical channel structure and the vertical channel structure are formed in a hole partially overlapping the first opening and the second opening. The vertical channel structure is divided into two arc channel parts by the drain pillar structure and the source pillar structure. The gate structure surrounds the drain pillar structure, the source pillar structure and the vertical channel structure.

Memory device and method for manufacturing the same

A three-dimensional memory device includes a substrate, conductive layers and insulating layers, a storage layer, a first channel, a second channel and a first conductive plug. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The storage layer penetrates through the multi-layer stacked structure, and has a first string portion and a second string portion that are spaced from each other. The first channel is located on a lateral side of the first string portion. The second channel is located on a lateral side of the second string portion. The first channel and the second channel have an upper channel portion and a lower channel portion. The first conductive plug is interconnected between the upper channel portion and the lower channel portion.

Three dimensional memory device and method for fabricating the same

A three-dimensional AND type flash memory and a manufacturing method thereof includes steps below is provided. A stack structure includes a first insulating layer and a first sacrificial layer is formed. A first pillar structure through the stack structure includes a second insulating layer and a second sacrificial layer surrounded by thereof is formed. A second pillar structure through the stack structure includes a channel layer and an insulating pillar surrounded by thereof is formed. The second sacrificial layer is located on both sides of the channel layer. The first sacrificial layer is removed. A lateral opening exposing a portion of the second insulating layer and the channel layer is formed. A gate insulating layer surrounding the exposed second insulating layer and channel layer is formed in the lateral opening. A gate layer is filled in the lateral opening. A conductive layer is used to replace the second sacrificial layer.

Three-dimensional and flash memory and manufacturing method thereof

Disclosed herein is a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first through hole on a precursor substrate, in which the first through hole passes through the first dielectric layer; filling a sacrificial material in the first through hole; forming a second dielectric layer having a second through hole over the first dielectric layer, in which the second through hole exposes the sacrificial material in the first through hole, and the second through hole has a bottom width less than a top width of the first through hole; removing the sacrificial material after forming the second dielectric layer having the second through hole; forming a barrier layer lining sidewalls of the first and second through holes; and forming a conductive material in the first and second through holes.

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Miaoli County, Taiwan

Chih-Wei Hu