Fujitsu Corporation

Hal Computer Systems, Inc.

Chih-Wei David Chang

Nirmal Raj Saxena

Yolin Lih

Leon Kuo-Liang Peng

Joel Frederick Boney

Jaspal Kohli

Kioumars Dawallu

Jen-Hong Charles Chen

Ming-Ying Li

A computer system includes a central processing unit and a memory management unit having a plurality of functional units, such as a memory interface unit, a remote interface unit, a cache interface unit, and a translation unit. Each functional unit has a low priority error queue for storing error information for errors having a low priority. Some functional units also have a high priority error queue for storing error information for errors having a high priority error. Based on the status of the error queues, the memory management unit prioritizes and handles errors caused by hardware failures. For low priority errors, an interrupt request signal is sent to the central processing unit. For high priority errors, a RED ALERT signal is sent to the processing unit to cause the processing unit to give immediate attention to the error. For high priority error queue overflows, a failure signal is generated which causes the system to be halted and the contents of the system to be scanned out. Thus, errors are prioritized and handled accordingly.

Method and apparatus for prioritizing and handling errors in a computer system

A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (TLB) and, possibly, a translation table held in memory and implemented as a B-tree data structure. The TLB is initially searched for a translation for a specified input address. If exactly one valid entry of the TLB stores a translation for the specified input address then the output address corresponding to the specified input address is determined from the contents of that entry. Otherwise, the translation table is searched for a translation for the specified input address. If two or more valid entries of the TLB store a translation for the specified input address then these entries are invalidated. If a search of the translation table is required then the method involves the retrieval from the translation table, and insertion into the TLB, of a translation for the specified input address and possibly one or more translations for other input addresses that are stored together with the translation for the specified input address in one node of the B-tree implementing the translation table. During the insertion into the TLB of a translation for a particular input address that was retrieved from the translation table it is determined if there is exactly one valid entry in the TLB that stores a translation for the particular input address. If so, then the translation retrieved from the memory is inserted into that entry, thereby avoiding the creation of multiple TLB entries for the same input address.

Lookaside buffer for address translation in a computer system

A memory management unit (MMU) includes a translation lookaside buffer capable of simultaneously servicing three requests supplied to the MMU by an instruction cache and two data caches, respectively. Also, an arbiter selects one of several pending requests from sources of different priorities for immediate processing by the MMU, using a process which avoids undue delay in servicing requests from sources of lower priority.

Parallel access micro-TLB to speed up address translation

A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (TLB) and, possibly, a translation table held in memory and implemented as a B-tree data structure. The TLB is initially searched for a translation for a specified input address. If exactly one valid entry of the TLB stores a translation for the specified input address then the output address corresponding to the specified input address is determined from the contents of that entry. Otherwise, the translation table is searched for a translation for the specified input address. If two or more valid entries of the TLB store a translation for the specified input address, then these entries are invalidated. If the translation table must be searched then the method involves retrieving from the translation table, and inserting into the TLB, a translation for the specified input address and possibly one or more translations for other input addresses stored with the translation for the specified input address in one node of the B-tree implementing the translation table. When a particular input address retrieved from the translation table is inserted into the TLB, it is determined whether there is exactly one valid entry in the TLB that stores a translation for the particular input address If so, then the translation retrieved from the memory is inserted into that entry, and no multiple TLB entries for the same input address are created.

Lookaside buffer for inputting multiple address translations in a

A method and apparatus are disclosed for detecting and correcting errors in the data stored within the entries of a memory table. Each time data is entered into the memory table, an error code generator generates a corresponding error code using the data. This error code is stored in the memory table along with the corresponding data. When an entry in the memory table is read out, an error detector receives the outputted data and its corresponding error code and processes the data and the error code to determine whether the outputted data contains any errors. If the outputted data contains any errors, the outputted data and error code are sent to an error correction unit. In response, the correction unit attempts to find single and double bit errors in the data by way of a compact and efficient computer program. If either a single or double bit error is found, the error correction unit corrects the error or errors to derive a set of corrected data. This corrected data is then written back to the proper entry within the memory table to correct the error or errors in the data. Data errors within the memory table are thus detected and corrected.

Error detection and correction method and apparatus

A method and system are disclosed wherein error detection codes are used for detecting and handling hardware errors in a memory table. Before each address and associated data are entered into the memory table, an error detection code is generated for both the address and the data. The address, data, and corresponding error codes are stored in the same entry line in the memory table. When the table receives an input address from a CPU, the input address is compared to all of the addresses stored within the memory table. If any stored address matches the input address, the matched address is outputted along with its associated data and its corresponding error codes. The matched address and its associated data are each processed with its corresponding error code to determine whether the outputted address and data are identical to the address and data used to generate the error codes. If either the address or the data has been altered by a hardware error in the memory, an error signal is generated to indicate that the outputted information is invalid. This error signal causes the outputted information to be ignored. The hardware error is thus detected and tolerated. The memory table also includes a fault tolerant coherence table which contains physical addresses and corresponding error codes. Each address and corresponding error code in the coherence table is periodically outputted and processed by an error processor to check for possible errors. If an address in the coherence table contains an error, the address is invalidated. By periodically monitoring the coherence table, errors are detected and reliability is improved.

Growing community of inventors

Saratoga, CA, United States of America

Chih-Wei David Chang