Ememory Technology Inc.

Industrial Technology Research Institute

Silicon Optronics, Inc.

Macronix International Co., Ltd.

Solid State System Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Advanced Micro Devices Corporation

Ati Technologies Ulc

Faraday Technology Corporation

Sunplus Technology Co., Ltd.

Solid State Systems Co., Ltd.

Chih-Wei Chen

Cheng-Da Huang

Chih-Chun Chen

Chih-Hung Wang

Chia-Chiang Chang

Wen-Tung Hsu

Hann-Tsong Wang

Chia-Hung Hung

Chin-Ching Wu

Chun-Hao Kuo

Chih-Wei Hsu

Rahul Kumar Agarwal

Milind S Bhagavat

Chen-Der Tsai

Yin-Chang Chen

Chin-Jyi Wu

Fei Guo

Kuang-Huan Hsu

Chun-Hung Lu

Shih-Chan Huang

Shui-Tien Lin

Ting-Chung Hu

Yun-Chuan Tu

Chi-Hung Liu

Kuan-Hsun Chen

Tai-Yao Lee

Chieh-Tse Lee

Chun-Hsien Su

Jung-Chen Ho

Li-Jen Lee

Chung-Wen Ma

Ju-Xu Lee

Span Lu

Ping-Yu Kuo

Da-Yi Chang

Kun-Pei Li

Hsiu-Lan Ting

Po-Ping Wang

Chen-Yung Lin

Mao-Shing Sun

Kung-Cheng Tu

Tzer-Kun Lin

Wen-Tzong Hsieh

Tung-Hai Wu

Yen-Chin Lin

Hsin-Chung Wang

An image-sensing system for the efficient detection of defective pixels is shown. An arithmetic logic unit (ALU) determines a defective pixel candidate of an image sensor based on the first frame captured by the image sensor, performs a lower-part comparison on the defective pixel candidate based on the first frame, and performs an upper-part comparison on the defective pixel candidate based on the second frame captured by the image sensor. The defective pixel candidate is confirmed to be defective based on the first frame as well as the second frame. Only limited pixel data is buffered for the defective pixel detection.

Image-sensing system and detection and correction method for defective pixel

Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer and an interconnect chip at least partially encased in the first molding layer. The interconnect chip has a first side and a second side opposite the first side and a polymer layer on the first side. The polymer layer includes plural conductor traces. A redistribution layer (RDL) structure is positioned on the first molding layer and has plural conductor structures electrically connected to the plural conductor traces. The plural conductor traces provide lateral routing.

High density cross link die with polymer routing layer

A random code generator includes a differential cell array, a power circuit, a voltage detector, a control circuit and a read/write circuit. The power circuit provides a supply voltage to a node. The differential cell array includes plural differential cells. Each differential cell includes two sub-cells. The two sub-cells have process variations. During the enrollment, one sub-cell is programmed, and the other sub-cell is subjected to a program inhibition. In addition, a random code is generated according to the storage state of the differential cell.

Random code generator with differential cells and associated control method

A sensing circuit includes a sensing stage. The sensing stage includes a voltage clamp, a P-type transistor and an N-type transistor. The voltage clamp receives a first power supply voltage and generates a second power supply voltage. The source terminal of the P-type transistor receives the second power supply voltage. The gate terminal of the P-type transistor receives a cell current from a selected circuit of a non-volatile memory. The drain terminal of the N-type transistor is connected with the drain terminal of the P-type transistor. The gate terminal of the N-type transistor receives a bias voltage. The source terminal of the N-type transistor receives a ground voltage. In a sensing period, the second power supply voltage from the voltage clamp is fixed and lower than the first power supply voltage.

Sensing circuit with voltage clamp for non-volatile memory

An image processing method is provided. The method includes the steps of: receiving upper image data; calculating a first ratio using a target pixel and a plurality of first reference pixels in the upper image data; calculating a first diffusion coefficient according to the first ratio and a diffusion coefficient mapping equation; calculating a first pixel value of the target pixel according to the target pixel, the first reference pixels, and the first diffusion coefficient; receiving lower image data; calculating a second ratio using the target pixel and a plurality of second reference pixels in the lower image data, wherein the target pixel has the first pixel value; calculating a second diffusion coefficient according to the second ratio and the diffusion coefficient mapping equation; and calculating a second pixel value of the target pixel according to the target pixel, the second reference pixels, and the second diffusion coefficient.

Image processing method for defect pixel detection, crosstalk cancellation, and noise reduction

A memory cell includes a latch, two antifuse elements, and two select transistors. The latch is connected with a first node and a second node, and receives a first power voltage and a second power voltage. The latch is selectively enabled or disabled according to an enable line voltage. The first antifuse element is connected with the first node and an antifuse control line. The second antifuse element is connected with the second node and the antifuse control line. The gate terminal, the first drain/source terminal and the second drain/source terminal of the first select transistor are connected with a word line, the first node and a bit line, respectively. The gate terminal, the first drain/source terminal and the second drain/source terminal of the second select transistor are connected with the word line, the second node and an inverted bit line, respectively.

Memory cell and associated array structure

A power-up sequence protection circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. First terminals of the first transistor, the second transistor, and the fourth transistor are coupled for receiving a program voltage. A control terminal of the third transistor is used for receiving a device voltage. A second terminal of the fourth transistor is used for outputting the program voltage when the fourth transistor is turned on. When the program voltage is unexpectedly powered up while the device voltage is not powered up, the first transistor is turned on, the second transistor is turned off, and the fourth transistor is turned off so as to block the program voltage outputted from the second terminal of the fourth transistor.

Power-up sequence protection circuit for avoiding unexpected power-up voltage

A self-timed reset pulse generator includes a flip-flop, a tracking block, and a tracking circuit. The flip-flop receives an input signal and a feedback signal and outputting a reset signal. The tracking block has replicating cells coupled in series and replicates a structure in an external device. The tracking block has a first terminal and a second terminal. The first terminal and the second terminal are taking from the tracking block at a same location or two different locations. The tracking circuit unit receives the reset signal and receives the first terminal and the second terminal for respectively discharging the tracking block at the first terminal and sensing a voltage level at the second terminal as triggered by the reset signal. A track-out signal serving as the feed back signal is output to the flip-flop when the voltage level is less than or equal to a threshold.

Self-timed reset pulse generator and memory device with self-timed reset pulse generator

An image capture device with a reduced number of line buffers. Based on an nline of image data provided from an image sensor array and buffered data in the line buffers, a logic circuit determines defective candidates in an nline of image data. When the (n+p)line of image data is provided from the image sensor array, the logic circuit reexamines the defective candidates in the nline of image data, for defective-pixel compensation, based on the (n+p)line of image data and the buffered data in the plurality of line buffers. The buffered data in the line buffers contains the (n&#x2212;p)to (n&#x2212;1)lines of image data while the nline of image data is provided from the image sensor array, and contains the nto (n+p&#x2212;1)lines of image data while the (n+p)line of image data is provided from the image sensor array.

Image capture device, and defective pixel detection and correction method for image sensor array

The present invention provides an image-correction system, including an image-capture module, a first calculation module, a second calculation module and an output module. The image-capture module obtains an input image and a guide image. The first calculation module obtains a first correction image according to a first parameter and a second parameter, obtains the first parameter according to the mean value of the guide image, a variance value of the guide image, a mean value of the input image and a smooth function, and obtains the second parameter according to the first parameter, the mean value of the guide image and the mean value of the input image. The second calculation module obtains the ratio value of the mean value of the guide image and the variance value of the guide image. The output module outputs the first correction image.

Image-correction system and method

A one time programming non-volatile memory cell includes a first floating gate transistor with a single gate structure, an isolation transistor, and a select transistor. A first terminal of the first floating gate transistor is connected with a second control line. A floating gate of the first floating gate transistor is in a floating state. A first terminal of the isolation transistor is connected with a second terminal of the first floating gate transistor. An isolation gate of the isolation transistor is connected with an isolation line. A first terminal of the select transistor is connected with a second terminal of the isolation transistor. A second terminal of the select transistor is connected with a first control line. A select transistor of the select transistor is connected with a word line.

One time programming non-volatile memory cell

The invention provides a non-volatile memory cell structure and non-volatile memory apparatus using the same. The non-volatile memory cell structure includes a substrate, first to three wells and first to three transistors. The first to three wells are disposed in the substrate, and the first to three transistors are respectively forming on the first to three wells. The first to third transistors are coupled in series. Wherein, a control end of the first transistor is floated, a control end of the second transistor receives a bias voltage, and a control end of the third transistor is coupled to a word line signal. Moreover, the third well and the second cell are in same type, and the type of the first well is complementary to a type of the third well.

Non-volatile memory cell structure and non-volatile memory apparatus using the same

A sensing apparatus and data sensing method are provided. The sensing apparatus includes an initial circuit, a reference current generator and a sensing circuit. The initial circuit discharges a sensing end to a reference ground during a discharge period, and pre-charges the sensing end to a preset voltage level during a pre-charge period according to an output signal. The reference current generator draws a reference current from the sensing end. The sensing circuit senses a voltage level on the sensing end to generate the output signal. Wherein, the sensing end receives a cell current from a memory cell, and the pre-charge period is after the discharge period.

Sensing apparatus and data sensing method thereof

An image surveillance system and an image surveillance method are provided. The image surveillance method includes following steps. An image is captured, and at least one reference target is defined in the captured image. A monitored object in the image is identified. A distance between the monitored object and each of the at least one reference target is individually calculated. Whether to announce at least one warning is determined according to a relationship between at least one threshold and the distance.

Image surveillance system and image surveillance method

A surface treating method for treating a tooth surface and a surface treating device thereof are provided. First, a working gas is filled into a tube. Next, a voltage is provided to the working gas for exciting the working gas into plasma. After that, the plasma is discharged through an opening of the tube for contacting the tooth surface.

Surface treating device and surface treating method

Growing community of inventors

Hsinchu, Taiwan

Chih-Wei Chen