Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Tsung Yao

Kong-Beng Thei

Harry Chuang

Chien-Wen Chen

Ming-Jer Chiu

Heng-Kai Liu

Gwan Sin Chang

Harry-Hak-Lay Chuang

Sheng-Chen Chung

Cliff Hou

Jung-Hui Kao

Cheng-Hung Yeh

Chung Long Cheng

Mong Song Liang

Gary Shen

A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.

Wiring layout having differently shaped vias

A method and system for extracting the parasitic capacitance in an IC and generating a technology file for at least one or more IC design tools are provided. Parasitic extraction using the preferred method can significantly reduce field solver computational intensity and save technology file preparation cycle time. The network-based technology file generation system enables circuit designers to obtain a desired technology file in a timely manner. The common feature of the various embodiments includes identifying common conductive feature patterns for a given technology generation. Capacitance models created from the identified patterns are used to assemble the required technology files for IC design projects using different technology node and different process flows.

Method of generating technology file for integrated circuit design tools

A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.

3-dimensional device design layout

Method for improving design window

Growing community of inventors

Hsin-Chu, Taiwan

Chih-Tsung Yao