Industrial Technology Research Institute

Tsinghua University

Global Unichip Corporation

Spirox Corporation/national

Chih-Tsun Huang

Cheng-Wen Wu

Juin-Ming Lu

Yao-Hua Chen

Jing-Jia Liou

Jing-Reng Huang

Chun-Chen Chen

Che-Wei Hsu

Chuang Cheng

Chi-Feng Wu

Chun-Hung Lai

Chih-Wea Wang

Yu-Xiang Yen

Wan-Shan Hsieh

Wei-Shiang Lin

Yu-Tsao Hsing

Kao-Liang Cheng

Sau-Kwo Chiu

Jen-Chieh Yeh

Kuo-Liang Cheng

A processing element architecture adapted to a convolution comprises a plurality of processing elements and a delayed queue circuit. The plurality of processing elements includes a first processing element and a second processing element, wherein the first processing element and the second processing element perform the convolution according to a shared datum at least. The delayed queue circuit connects to the first processing element and connects to the second processing element. The delayed queue circuit receives the shared datum sent by the first processing element, and sends the shared datum to the second processing element after receiving the shared datum and waiting for a time interval.

Processing elements array that includes delay queues between processing elements to hold shared data

An adaptive learning power modeling method includes: sampling at least one of a plurality of network components to form a power consumption evaluation network according to at least one parameter within a parameter range; evaluating a predictive power consumption of a to-be-measured circuit by the power consumption evaluation network; training and evaluating an actual power consumption and the predictive power consumption of the to-be-measured circuit by the power consumption evaluation network to obtain an evaluation result; and performing training according to the evaluation result to determine whether to change the power consumption evaluation network.

Hardware structure aware adaptive learning based power modeling method and system

A DNN hardware accelerator and an operation method of the DNN hardware accelerator are provided. The DNN hardware accelerator includes: a network distributor for receiving an input data and distributing respective bandwidth of a plurality of data types of a target data amount based on a plurality of bandwidth ratios of the target data amount; and a processing element array coupled to the network distributor, for communicating data of the data types of the target data amount between the network distributor based on the distributed bandwidth of the data types.

Deep neural networks (DNN) hardware accelerator and operation method thereof

A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.

Memory transaction-level modeling method and system

A probing system for an integrated circuit device, which transmits a testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system includes a test head having a first transceiving module. There is a test station having a test unit coupled to the test head to perform a test operation. A communication module has a second transceiving module configured to exchange data with the first transceiving module in a wireless manner. There is an integrated circuit device having a core circuit being tested, and a test module having a self-test circuit coupled to the core circuit and the communication module for performing the core circuit self-testing.

Probing system for integrated circuit devices

In a method of testing a multi-port memory in accordance with a test pattern, test clock signals having the same test clock frequency but with different delay periods introduced therein are generated for controlling memory access through the different access ports of the memory. Consecutive memory operations of a test element of the test pattern are then conducted in a folded sequence upon a memory cell through the different access ports in accordance with the test clock signals such that the memory operations are completed within the same test clock cycle of the test element.

Multi-port memory testing method utilizing a sequence folding scheme for testing time reduction

The present invention discloses a diagonal testing method for flash memories. The testing method regards the flash memory as several squares, and executes in the direction from top to bottom and from left to right. Each square is provided with a first diagonal in &#x2212;45 degrees from the upper left to the lower right, and a second diagonal in +45 degrees from the lower left to the upper right. The present invention is to program the cells in the first diagonal or the second diagonal, and then read the cells except the first diagonal or the second diagonal; or, program the cells except the first diagonal or the second diagonal, and then read the cells in the first diagonal or the second diagonal so as to detect the disturb fault in the flash memories and normal memory fault models.

Diagonal testing method for flash memories

A test pattern generation and comparison circuit creates test pattern stimulus signals for and evaluates response signals from logic or memory such as random access memory (RAM). It utilizes both parallel and serial interfaces to the logic/memory under test. The test pattern generation and comparison circuit further provides a method for testing logic and memory utilizing built-in self test (BIST) techniques. The method uses a programmable logic/memory commands which are translated into physical logic signals and timings for the logic or memory under test. The results of the test pattern generated and applied to the logic or memory are compared to expected results. The result of the comparison is a pass/fail designation. In addition, the comparison of the expected test results with the actual test results provides information on the exact location of the failure. Also, since the test pattern generation and comparison circuit architecture is compatible with hardware description languages such as Verilog HDL or VHDL, the test pattern generation and comparison circuit can be automatically generated with a silicon compiler.

Test pattern generator for SRAM and DRAM

In the present invention a built in self test (BIST) for an embedded memory is described. The BIST can be used at higher levels of assembly and for commodity memories to perform functional and AC memory tests. A BIST controller comprising a finite state machine is used to step through a test sequence and control a sequence controller. The sequence controller provides data and timing sequences to the embedded memory to provide page mode and non-page mode tests along with a refresh test. The BIST logic is scan tested prior to performing the built in self test and accommodations for normal memory refresh is made throughout the testing. The BIST also accommodates a burn-in test where unique burn-in test sequences can be applied.

Growing community of inventors

Hsinchu, Taiwan

Chih-Tsun Huang