Amazing Microelectronic Corporation

Industrial Technology Research Institute

Chih-Ting Yeh

Che-Hao Chuang

Yung-Chih Liang

Sung-Chih Huang

Kun-Hsien Lin

Shih-Hung Chen

Che-hao Chuang

Sung Chih Huang

A transient voltage suppressor with adjustable trigger and holding voltages is provided, including a heavily doped substrate of a first conductivity type connected to a first node, a lightly doped epitaxial layer of a second conductivity type on the substrate, a first and third well region of the first conductivity type, a second well region of the second conductivity type, a first and third heavily doped region of the second conductivity type and a second heavily doped region of the first conductivity type. The heavily doped regions are commonly electrically connected to a second node, and individually disposed in the well regions. Trenches are disposed opposite in the substrate for electrical isolation. A floating base bipolar junction transistor and silicon controlled rectifier can be respectively formed under a positive and negative surged mode. Accordingly, the invention is advantageous of superior electrical performances, high layout flexibility and low area consumption.

Transient voltage suppressor with adjustable trigger and holding voltages

A diode test module and method applicable to the diode test module are provided. A substrate having first conductivity type and an epitaxial layer having second conductivity type on the substrate are formed. A well region having first conductivity type is formed in the epitaxial layer. A first and second heavily doped region having second conductivity type are theoretically formed in the well and connected to a first and second I/O terminal, respectively. Isolation trench is formed there in between for electrical isolation. A monitor cell comprising a third and fourth heavily doped region is provided in a current conduction path between the first and second I/O terminal when inputting an operation voltage. By employing the monitor cell, the invention achieves to determine if the well region is missing by measuring whether a leakage current is generated without additional testing equipment and time for conventional capacitance measurements.

Diode test module for monitoring leakage current and its method thereof

A transient voltage suppression device includes at least one diode string, a power clamp device, at least one first bypass diode, and at least two second bypass diodes. The diode string is coupled between a power terminal and a common bus and coupled to an input output (I/O) port. The power clamp device is coupled between the power terminal and the common bus. The first bypass diode is coupled between the common bus and a ground terminal. The second bypass diodes are coupled in series, coupled between the common bus and the ground terminal, and coupled to the first bypass diode in reverse parallel. Alternatively, the first bypass diode and the second bypass diodes are replaced with at least one bi-directional electrostatic discharge (ESD) device.

Transient voltage suppression device

A vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one doped well, an isolation structure, and an external conductor. The heavily-doped semiconductor substrate and the doped well have a first conductivity type, and the first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The doped well is formed in the first semiconductor epitaxial layer. The isolation structure, formed in the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer, surrounds the first semiconductor epitaxial layer and the at least one doped well. The external conductor is arranged outside the first semiconductor epitaxial layer and the doped well and electrically connected to the first semiconductor epitaxial layer and the doped well.

Vertical bipolar transistor device

A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.

Floating base silicon controlled rectifier

A vertical bipolar transistor device is disclosed. The vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one first doped well, and an external conductor. The heavily-doped semiconductor substrate and the first doped well have a first conductivity type. The first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The first doped well is formed in the first semiconductor epitaxial layer. The external conductor is arranged outside the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer and electrically connected to the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer.

A lateral transient voltage suppressor device is provided, comprising a doped substrate, a lateral clamping structure disposed on the doped substrate, a buried doped layer disposed between the doped substrate and the lateral clamping structure for isolation, at least one diode module, and at least one trench arranged in the doped substrate, having a depth not less than that of the buried doped layer, and being disposed between the lateral clamping structure and the at least one diode module for electrical isolation. The doped substrate and the buried doped layer have opposite conductivity types such that the doped substrate is electrically floating. The buried doped layer can be further disposed to separate the diode module from the doped substrate. By employing the proposed invention, the lateral transient voltage suppressor device is advantageous of maintaining both a lower clamping voltage as well as a reduced dynamic resistance.

Lateral transient voltage suppressor device

A circuit and a method for electrostatic discharge clamping are provided. The circuit includes a detection module, a control module, and a clamping module. The detection, control, and clamping modules are coupled with a first power line of a first power source and a second power line of the first power source. Third terminals of the detection, control and clamping modules are coupled to a first power line of a second power source, a voltage division terminal of the detection module, a fourth terminal of the control module respectively. According to an electrostatic discharge event on the first power line of the first power source, the division voltage terminal of the detection module provides a voltage to the control module. Then, the control module controls the clamping module to couple the first power line of the first power source to the second power line of the first power source.

Circuit and method for electrostatic discharge clamping

A heat-dissipating Zener diode includes a heavily-doped semiconductor substrate having a first conductivity type, a first epitaxial layer having the first conductivity type, a first heavily-doped area having a second conductivity type, a second epitaxial layer, and a second heavily-doped area having the second conductivity type or the first conductivity type. The first epitaxial layer is formed on the heavily-doped semiconductor substrate. The first heavily-doped area is formed in the first epitaxial layer and spaced from the heavily-doped semiconductor substrate. The second epitaxial layer is formed on the first epitaxial layer and penetrated with a first doped area, and the first doped area has the second conductivity type and contacts the first heavily-doped area. The second heavily-doped area is formed in the first doped area.

Heat-dissipating Zener diode

One embodiment of the disclosure provides an electrostatic discharge protection circuit. The electrostatic discharge protection circuit includes a p-type field effect transistor, a capacitance device and an n-type field effect transistor. The p-type field effect transistor has a source coupled to an input/output terminal, a gate coupled to a first node and a drain coupled to a second node. The capacitance device has a first terminal coupled to a first rail and a second terminal coupled to the first node. The n-type field effect transistor has a source coupled to the first rail, a gate coupled to the second node and a drain coupled to the first node.

ESD protection circuit

An electrostatic discharge (ESD) protection apparatus, coupled between a first rail line and a second rail line, includes a clamp circuit and a detection circuit. The detection circuit includes an electronic element having an equivalent capacitance value, and a transistor having a gate, a first input and a second input respectively coupled to a first node, the first rail line and a drive terminal of the clamp circuit. In response to an ESD event, leakage currents pass between the first input and the gate and between the second input and the gate to equivalently form parasitic resistance therein, respectively. The parasitic resistances and the electronic element form a delay circuit to provide a drive voltage between the gate and the first input, and to provide a trigger current for conducting the clamp circuit, so that the first and second rail lines perform an ESD operation via the clamp circuit.

Electrostatic discharge protection apparatus and associated method

One embodiment of the disclosure provides an electrostatic discharge protection circuit, including a first resistor, a p-type field effect transistor, a capacitance device and an n-type field effect transistor. The first resistor has a first terminal coupled to a first rail and a second terminal coupled to a first node. The p-type field effect transistor has a source coupled to the first rail, a gate coupled to the first node and a drain coupled to a second node. The capacitance device has a first terminal coupled to a second rail or the second node and a second terminal coupled to the first node. The n-type field effect transistor has a source coupled to the second rail, a gate coupled to the second node and a drain coupled to the first node.

An electrostatic discharge (ESD) protection apparatus includes a clamp circuit, a detection circuit and a control circuit. The clamp circuit has a first terminal and a second terminal respectively coupled to a first rail line and a second rail line. In response to an ESD event, the clamp circuit generates a first coupling potential at its coupling terminal. The detection circuit, coupled to the coupling terminal of the clamp circuit and the second rail line, outputs a detection signal in response to the first coupling potential. The control circuit, coupled to the first and second rail lines, the detection circuit and the clamp circuit, outputs a conduction signal to a control terminal of the clamp circuit in response to the detection signal. The clamp circuit is conducted in response to the conduction signal so that ESD between the first and second rail lines is performed through the clamp circuit.

Electrostatic discharge protection apparatus and method therefor

An electrostatic discharge (ESD) clamp circuit is provided. The ESD clamp circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a third transistor. A clamp device of the ESD clamp circuit is implemented by the third transistor. A parasitic capacitor of the third transistor forms a detection scheme along with the second resistor to detect the ESD. The first resistor, the second resistor, the first transistor, and the second transistor form a feedback scheme to control the third transistor for discharging the ESD current.

Growing community of inventors

Hsinchu County, Taiwan

Chih-Ting Yeh