Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Ting Sun

Tseng Chin Lo

Bo-Sen Chang

Molly Chang

Geng-He Lin

Ya-Wen Tseng

Zi-Kuan Li

Kung-Cheng Lin

Yueh-Yi Chen

Ying-Jung Chen

Meng Lin Chang

Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.

Method of measuring mask overlay using test patterns

Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.

Integrated circuit filler and method thereof

Integrated circuit overlay test patterns and method thereof

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Hsinchu County, Taiwan

Chih-Ting Sun