Cirrus Logic Inc.

Intel Corporation

Chih-Ta Sung

Tzoyao Chan

Richard Chang

Jih-Hsien Soong

Yuanyuan Sun

Daniel Thomas Daum

Chia-Lun Hang

Jeffrey G Ort

Mark A Rosenau

Jerry G Jex

Alan E Baker

A multimedia system includes an audio/video decompresser/decoder for decompressing/decoding a compressed/encoded audio/video data stream in order to generate video images for display on a display device and to generate audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder that has a novel memory controller and a novel method for displaying complete decoded/decompressed video frames on a display device without tearing. By use of selective storage of decoded/decompressed video frames in memory, tearing is prevented but information for predicting motion of a video segment is preserved.

Memory controller for decoding a compressed/encoded video data frame

A multimedia system including an audio/video decoder/decompresser for decoding/decompressing a compressed encoded audio/video data stream to generate video images for display and audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder with an audio/video synchronization circuit for substantially synchronizing the display of video images with audio playback. In addition, a step control is provided to allow for viewing of video images on a frame-by frame basis or to freeze or play video in slow motion. When step control is activated, audio output is muted. Audio data corresponding to displayed video is transmitted to the muted audio decoder. An internal system clock may be suppressed to the system clock counter. An external CPU may provide system clock start times corresponding to video frames to be displayed. The external CPU may increment the system clock counter by a an amount corresponding to the difference between a successive frame or number of frames. When nominal playback is resumes, the audio and video data streams are substantially in synchronization.

Stream synchronization method and apparatus for MPEG playback system

An automatic bus identification circuit is provided in a device to reliably detect system bus type on power up despite fluctuations in supply voltage. A system bus type signal is received over a multi-function input line at a first input and a reset signal received over a set line at a second input. A bus type identification circuitry is provided to latch the system bus type signal upon power up and continuously output this signal as a system bus type identification signal. To prevent the influence of disturbances in the power supply upon power-up, a flip-flip is provided to output a logic signal in response to a system reset signal. The flip-flop is configured with a strong-N type inverter to insure that the flip-flop will be set into a grounded state as power is applied to the circuit, despite the influence of transient power supply voltages.

Reset based computer bus identification method and circuit resilient to

A multimedia system including an audio/video decoder/decompresser for decoding/decompressing a compressed encoded audio/video data stream to generate video images for display and audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder with an audio/video synchronization circuit for substancially synchronizing the display of video images with audio playback. A method is described for detecting when the playback of audio and the display of video images are out of synchronization. The circuitry includes three programmable registers, a finite state machine and one full adder using an audio presentation time stamp and the video presentation time stamp. The method uses a rounded programmable bias value which is compared with the difference between the video presentation time stamp and the audio presentation time stamps. The difference may included the latency delay of the audio and video display devices to more properly reflect the synchronization status between audio and video. The circuit area used by the circuitry has been minimized by selective rounding or truncation of the audio presentation time stamp and the video presentation time stamp without sacrificing the accuracy or speed of determining the synchronization between audio and video.

Programmable audio-video synchronization method and apparatus for

A low power bias voltage generation circuitry for content addressable memory cells for a nonvolatile memory is described. The bias circuitry is comprised of a source follower pair and two cascaded high impedance voltage dividers. The source follower pair acts as a positive feedback loop coupling between the two high impedance voltage dividers for relatively quickly charging and settling the output node to a predetermined voltage level. The first high impedance voltage divider can relatively quickly provide an input signal to trigger the small-input-load second high impedance voltage divider. The second high impedance voltage divider comprised of two high impedance diode stacks allows most current drawing from the power supply to drive a relatively large output loading during switching. Both first and second high impedance voltage dividers help keep the DC current of the circuit to a relatively low level which helps to reduce the total power consumption of the circuit.

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Princeton, NJ, United States of America

Chih-Ta Sung