Siemens Aktiengesellschaft

Hewlett-packard Company

Chih-Ta Star Sung

Venkat Mattela

Muhammad Afsar

Balraj Singh

Chih-Teng Hung

Lyle Albertson

An apparatus and method are disclosed for activating a memory location within a memory device. In an apparatus aspect of the invention, a memory device is disclosed. The memory device includes an enable unit arranged to receive a plurality of address signals and a clock signal and to output an activation signal. The address signals has an associated worst case delay, and the enable unit is further arranged to generate an enable signal that is delayed from the clock signal by at least about the worst case delay. The memory device further includes a memory array arranged to receive the activation signal in response to which a corresponding memory location is activated.

Memory activation devices and methods

An electronic memory. The electronic memory includes memory cells and corresponding reference memory cells. Wordlines are connected to the memory cells and the corresponding reference memory cells. If an accessed memory cell has previously been programmed to a first state, an output from the memory cell is connected to a bitline. An output from a selected reference memory cell is connected to a reference bitline. The bitline and the reference bitline are connected to a differential input sense amplifier. The differential input sense amplifier detects the voltage differential between the bitline and the reference bitline. If the memory cell is accessed and the memory cell is in the first state, the memory cell drives the voltage potential on the bitline from a precharge voltage to a discharge voltage at a first rate. If the memory cell is selected and the memory cell is in a second state, the memory cell does not effect the voltage potential on the bitline and the voltage potential on the bitline remains at the precharge voltage. If the reference memory cell is selected, the reference memory cell drive the voltage potential on the reference bitline from the precharge voltage to the discharge voltage at a second rate. The first rate is faster than the second rate. Therefore, if the selected memory cell is in the first state, the differential sense amplifier will output a first voltage level. If the selected memory cell is in the second state, the differential amplifier will output a second voltage level.

High speed, low noise, low power, electronic memory sensing scheme

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Princeton, NJ, United States of America

Chih-Ta Star Sung