Siliconware Precision Industries Co., Ltd.

Chih-Shun Chen

Ke-Chuan Yang

Feng-Lung Chien

Po-Hao Yuan

Shih-Kuang Chiu

Chi-Chuan Wu

Jui-Meng Jao

Chao-Dung Suo

An improved tape carrier package (TCP) structure is proposed, which is characterized in the provision of dummy pads and dummy leads to help reinforce the package construction. The dummy pads are provided on the corners of the semiconductor chip, while the dummy leads are bonded between the dummy pads and corner-situated lead-bonding areas on the tape carrier. During assembly, since dummy leads are bonded between the dummy pads and corner-situated lead-bonding areas, the corners of the semiconductor chip can be firmly supported as well as the four sides of the semiconductor chip which are supported by the I/O leads. As a result the package construction is reinforced. During inner-lead bonding (ILB) process, such reinforcement can help prevent the cracking of the I/O leads. Moreover, during encapsulation process, the provision of the dummy leads can help allow the encapsulation material to be more evenly distributed to the back side of the semiconductor chip, thus preventing undesired forming of voids in the resulted encapsulation body, making the resulted encapsulation body less likely subjected to popcorn effect and delamination. In addition, it can help provide a uniform package height (UPH) to the overall package construction. These advantages allow the finished TCP product to be more assured in quality and reliability.

Tape carrier package structure with dummy pads and dummy leads for package reinforcement

A flip-chip bumping method is proposed for the fabrication of solder bumps on a semiconductor wafer for flip-chip application. The proposed flip-chip bumping method is intended for use on a semiconductor wafer predefined with a plurality of chip regions which are delimited from each other by a predefined cutting line and each of which is formed with a plurality of aluminum or copper based bond pads, and is characterized in the provision of a plating bus over and along the cutting line and connected to each bond pad. By means of this plating bus, the required UBM (Under Bump Metallization) fabrication and solder-bump fabrication can be both carried out through plating. Since plating process is considerably lower in cost than sputtering process and etching process, the proposed flip-chip bumping method can be more cost-effective to implement than prior art.

Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer

A solder-pump fabrication method is proposed, which is used for the fabrication of solder bumps with high coplanarity over a semiconductor chip for flip-chip application. The proposed solder-bump fabrication method is characterized in the use of a two-step solder-bump fabrication process, including a first step of electroplating solder over UBM (Under Bump Metallization) pads to a controlled height still below the topmost surface of the mask, and a second step of screen-printing solder paste over the electroplated solder layer. The combined structure of the electroplated solder layer and the printed solder layer is then reflowed to form the desired solder bump. Since the proposed solder-bump fabrication method allows the solder material electroplated and printed over the UBM pads to be confined within the mask openings and never exceed the topmost surface of the mask, the resulted solder bumps would not be bridged to neighboring ones. Moreover, the proposed solder-bump fabrication method allows all the resulted solder bumps to be substantially equally sized to achieve high coplanarity.

Method of fabricating solder bumps with high coplanarity for flip-chip application

Growing community of inventors

Kaohsiung, Taiwan

Chih-Shun Chen