Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih Sheng Tsai

Chung-Hsing Wang

Shu Yi Ying

Lee-Chung Lu

Yi-Kan Cheng

Hsiao-Shu Chao

Ho Che Yu

Kai-Yun Lin

Ying-Lin Liu

Chin-Yu Chiang

Chih-Chieh Chen

Chen-Fu Huang

Chen-Fu “Alex” Huang

An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

Optimization for circuit migration

An embodiment is a method for providing an adjusted electronic representation of an integrated circuit layout, the method including using one or more processor, generating a timing performance of a path in a first netlist, identifying a first cell in the path that violates a timing performance parameter, and generating a plurality of derivative cells from a subsequent cell that is in the path after the first cell, where each derivative cell includes a variation of the subsequent cell. The method further includes in response to the identifying the first cell, replacing the subsequent cell with at least one of the plurality of derivative cells to generate a first modified netlist, where the variation of the at least one of the plurality of derivative cells reduces the violation of the timing performance parameter, and generating a final netlist based on the first modified netlist.

A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers.

Verification of 3D integrated circuits

Circuits and methods for providing a pulsed clock signal for use with pulsed latch circuits are described. A variable pulse generator is coupled to form a pulsed clock output responsive to a control signal and a clock input signal. A feedback loop is provided with a pulse monitor and a pulse control circuit. Samples of the pulsed clock signal are taken by the pulse monitor and an output is formed in the form of a pattern. The pulse control circuit receives the output of the monitor and determines whether it matches a predetermined pattern. Adjustments are made to the control signal to adaptively adjust the pulsed clock signal. The feedback loop may operate continuously. In alternative embodiments the feedback loop may be powered down. Methods for adaptively controlling a pulsed clock signal are disclosed.

Clock circuit and method for pulsed latch circuits

A method of designing a 3D integrated circuit (3D IC) including providing a first layout corresponding to a first device of a 3D IC and a second layout corresponding to a second device of a 3D IC is provided. A verification, such as LVS or DRC, may be performed not only on each device separately, but may also be performed to ensure proper connectivity between devices. The verification may be performed on a single layout file (e.g., GDS II file) including the interface layer of the first and second die. Dummy feature pattern may be determined for the 3D IC using a layout including the interface layers of the first and second devices.

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Taichung County, Taiwan

Chih Sheng Tsai