Industrial Technology Research Institute

Chih Sheng Lin

Keng-Li Su

Chih-Wen Hsiao

Min-Chuan Wang

Min Chuan Wang

Keng Li Su

Wei Chun Chang

A monitoring method of a three-dimensional integrated circuit (3D IC) is provided, wherein the method includes: providing a plurality of TSVs, providing a plurality of inverters; connecting the inverters with the plurality of TSVs as a circuit loop; enabling the circuit loop to oscillate; measuring an output signal on an output end of one of the plurality of inverters; and determining the manufacturing state of the plurality of TSVs of the 3D IC based on the output signal and apparatus using the same.

Monitoring method for three-dimensional intergrated circuit (3D IC) and apparatus using the same

A monitoring method for Through-Silicon Vias (TSVs) of a three-dimensional integrated circuit (3D IC) is provided, wherein the 3D IC includes a plurality of TSVs, and the method includes: providing a plurality of inverters; connecting the inverters with the TSVs as a circuit; enabling the circuit to oscillate; measuring an output signal on an output end of one of the inverters; and determining the characteristic of TSVs of the 3D IC based on the output signal.

Monitoring method for through-silicon vias of three-dimensional intergrated circuit (3D IC) and apparatus using the same

A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level.

Memories with improved write current

The present invention relates to a memory accessing circuit, which is for accessing a memory circuit with 2impedance states. The memory accessing circuit includes a testing signal generating circuit, for generating a testing signal by detecting the impedance state of the memory circuit; a reference signal generating circuit, for generating 2reference signals by detecting the impedance states of a reference circuit having 2impedance paths; a median signal generating circuit, for generating (2)&#x2212;1, median signals by receiving the 2reference signals; and a comparing circuit, for comparing the testing signal and the (2) median signals. The present invention further provides a memory accessing method thereof.

Growing community of inventors

Tainan County, Taiwan

Chih Sheng Lin