Industrial Technology Research Institute

National Yang Ming Chiao Tung University

Ubilux Optoelectronics Corporation

Apex Biotechnology Corporation

Chih-Sheng Lin

Sih-Han Li

Shyh-Shyuan Sheu

Jian-Wei Su

Fu-Cheng Tsai

Tuo-Hung Hou

Keng-Li Su

Yu-Hui Lin

Kuan-Wei Chen

Zhe-Hui Lin

Pei-Ling Tseng

Chia-Pao Chang

Erh-Hao Chen

Hsin-Chi Lai

Ya-Wen Yang

Shih-Chieh Chang

Ra-Min Tain

Ming-Ji Dai

Shih-Hsien Wu

Kai-Tai Song

Heng-Yuan Lee

Kuo-Hua Tseng

Thomas Y S Shen

Jan-Ruei Lin

Chih-Wen Hsiao

Yueh-Hui Lin

Chih-Ping Cheng

Sz-Hau Chen

Tay-Jyi Lin

Pi-Feng Chiu

Chih-Ming Lai

Min-Chuan Wang

Yi-Ching Kuo

Shun-Hong Zheng

Guan-Tin Chen

Chia-Hao Lin

Su-Hen Yang

Che-Hsiung Wu

Chiu-Mei Kuo

Yi-Chun Yang

Wen-Xin Zhang

Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.

Memory cell

A data feature augmentation system and method for a low-precision neural network are provided. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used for receiving an input signal and obtaining a first signal according to the input signal. The first signal is related to a first leakage rate of the first sample-and-hold circuit and the first signal is the signal generated by delaying the input signal by one time unit. The subtractor is used for performing subtraction on the input signal and the first signal to obtain a time difference signal. The input signal and the time difference signal are inputted to the low-precision neural network.

Data feature augmentation system and method for low-precision neural network

According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

Memory circuit with sense amplifier calibration mechanism

A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

Computing in memory cell

A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values. The comparator compares the accumulated data weight value with the reference value(s) to generate a data weight state.

Memory device and data weight state determining method for in-memory computation

Provided is a continuous microalgae culture module, including an outdoor culture unit, a high-density culture unit, a pigment induced unit, and a harvesting unit. A method of culturing microalgae containing macular pigment is also provided, including sequentially culturing microalgae with medium in the outdoor culture unit and the high-density culture unit, producing macular pigment in the pigment induced unit through different light irradiation, and collecting the microalgal biomass containing macular pigment in the harvesting unit.

Continuous microalgae culture module and method of culturing microalgae containing macular pigment

A computation operator in memory and an operation method thereof are provided. The computation operator in memory includes a word line calculator, a decision-maker and a sense amplifier. The word line calculator calculates a number of enabled word lines of a memory. The decision-maker generates a plurality of reference signals according to at least one of the number of enabled word lines and a used size of the memory, the reference signals are configured to set a distribution range. The sense amplifier receives a readout signal of the memory, and obtains a computation result by converting the readout signal according to the reference signals.

Computation operator in memory and operation method thereof

A readout circuit for a sensor and a readout method thereof are provided. The readout circuit includes a reference circuit, a compensated circuit, and a signal processing circuit. The reference circuit provides a direct current (DC) signal. The compensated circuit is coupled to the reference circuit. The compensated circuit obtains an analog sensing signal of the sensor, obtains the DC signal from the reference circuit, and provides a compensated signal according to the analog sensing signal and the DC signal. The signal processing circuit is coupled to the compensated circuit. The signal processing circuit processes the compensated signal to convert the compensated signal into a digital sensing signal. The compensated circuit subtracts the DC signal from the analog sensing signal to provide the compensated signal.

Readout circuit for sensor and readout method thereof

A method of manufacturing a sensor device is provided. In the method, sensing electrodes are formed on a substrate, a sensing material layer is formed on the sensing electrodes. The sensing material layer is etched to form a first nanowire sensing region, a second nanowire sensing region and a third nanowire sensing region respectively between every two sensing electrodes of the sensing electrodes. A dielectric layer is formed to cover the first nanowire sensing region, the second nanowire sensing region and the third nanowire sensing region, and the first nanowire sensing region and the third nanowire sensing region are exposed.

Method of manufacturing sensor device

A sensor device and a method of manufacturing the same are provided. The sensor device includes a substrate, a plurality of sensing electrodes, a humidity nanowire sensor, a temperature nanowire sensor, and a gas nanowire sensor. The sensing electrodes are formed on the substrate, and the humidity, the temperature and the gas nanowire sensors are also on the substrate. The humidity nanowire sensor includes an exposed first nanowire sensing region, the temperature nanowire sensor includes a second nanowire sensing region, and the gas nanowire sensor includes a third nanowire sensing region.

Sensor device and method of manufacturing the same

A sensor interface circuit and sensor output adjusting method are provided. The sensor interface circuit includes a processor and a gain control circuit. The processor obtains information of a linear region of a sensor to set a configuration corresponding to the sensor. The gain control circuit is coupled to the processor, performs a return-to-zero operation for a maximum electronic value and a minimum electronic value corresponding to the linear region and performs a full-scale operation for a slope of the linear region according to the maximum input range of an analog-to-digital converter which is a subsequent-stage circuit of the sensor interface circuit.

Sensor interface circuit and sensor output adjusting method

First and second paths of the primary-coil of the transformer are located at different sides of the symmetry-line. First terminals of the first and second paths are first and second ports of the primary-coil. Second terminals of the first and second paths are connected to each other. Two partial paths of the first path are connected to each other by TSV. Two partial paths of the second path are connected to each other by TSV. Third and fourth paths of the secondary-coil of the transformer are located on different sides of the symmetry-line. First terminals of the third and fourth paths are first and second ports of the secondary-coil. Second terminals of the third and fourth paths are connected to each other. Two partial paths of the third path are connected to each other by TSV. Two partial paths of the fourth path are connected to each other by TSV.

Three-dimension symmetrical vertical transformer

TSV repair circuit of a semiconductor device includes a first chip, a second chip, at least two TSV, at least two data path circuits and an output logic circuit. Each data path circuit comprises an input driving circuit, a TSV detection circuit, a memory device, a protection circuit and a power control circuit. The TSV detection circuit detects a TSV status, the memory device keeps the TSV status, the protection circuit determines whether to pull a first end of the TSV to a ground voltage according to the TSV status, and the power control circuit prevents a leakage current of a power voltage from flowing through a substrate.

Through silicon via repair circuit of semiconductor device

A testing and repairing apparatus of through silicon via (TSV) disposed between a first and a second chips is provided. First terminals of a first and a second switches are coupled to a first terminal of the TSV. First terminals of a third and a fourth switches are coupled to a second terminal of the TSV. A first terminal of a first resister is coupled to a first voltage. A first selector is coupled between second terminals of the second switch and the first resister. A second selector is coupled between a second terminal of the fourth switch and a second voltage. A first control circuit detects the second terminal of the second switch, and controls the first switch, the second switch and the first selector. A second control circuit controls the third switch, the fourth switch and the second selector.

Growing community of inventors

Tainan, Taiwan

Chih-Sheng Lin