United Microelectronics Corp.

Himax Technologies, Inc.

Sea Sonic Electronics Co., Ltd.

Chih-Sheng Chang

Yuan-Fu Ko

Ching-Chih Chang

Ching-Li Yang

Sheng-Chien Chou

Shih-Che Huang

Meng-Ko Tsai

Tsung-Yin Hsieh

Min-Shiang Hsu

Yu-Han Tsai

Tzu-Hao Fu

Teng-Te Huang

Kun-Chen Ho

Shih-Chun Tsai

Shih-Hsien Chen

Yi-How Chou

Yang-Chou Lin

Chen-Yi Weng

Yin-Dong Lu

Chi-Rong Lin

Shu-Hao Hsu

Chun-Wei Kang

Bo-Wei Huang

Ho-Yu Lai

Teng Te Huang

Chung-Kai Sheng

Jun-Yu Zhan

Yi-Hsiu Chen

Yu-Cheng Tung

Chien-Ting Lin

Yu-Hsiang Lin

Yu-Tsung Lai

Han-Yi Kuo

Yi-Tyng Wu

Jun-Chi Huang

Wei-Chih Chen

Meng-Jun Wang

Cheng-Yung Lo

Shi-Jen Wu

Ci-Dong Chu

Hui-Lung Chou

Chih-Jen Lin

Tung-Ming Chen

Chun-Hsing Tung

Huai-Hsuan Tsai

Hung-Wei Yang

Jen-Hui Lai

Ting-Chun Wang

Chung-Hsien Tsai

Nien-Chung Chiang

Nien-Chung Jiang

A diffractive optical element and method for fabricating the diffractive optical element are provided. The diffractive optical element includes a substrate, a first diffractive structure layer and a second diffractive structure layer. The substrate has a first surface and a second surface opposite to the first surface. The first diffractive structure layer is disposed on the first surface of the substrate. The second diffractive structure layer is disposed on the second surface of the substrate. In the method for fabricating the diffractive optical element, at first, the substrate is provided. Then, a first glue material layer/first semiconductor layer is formed and patterned on the first surface of the substrate. Thereafter, a second glue material layer/second semiconductor layer is formed and patterned on the second surface of the substrate.

Diffractive optical element and method for fabricating the diffractive optical element

A semiconductor device includes a first metal interconnection disposed on a substrate, a second metal interconnection disposed on the first metal interconnection, a first contact via disposed between the first metal interconnection and the second metal interconnection, a first serpent metal line connecting to a first end of the first metal interconnection, and a second serpent metal line connecting to a second end of the first metal interconnection. Preferably, the first serpent metal line, the second serpent metal line, and the first metal interconnection are on a same level.

Metal interconnect structure having serpent metal line

A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, a seal ring structure including first and second interconnect structures, and a passivation layer on the seal ring structure and the second dielectric layer. The first interconnect structure is located in the first dielectric layer. The second interconnect structure is located in the second dielectric layer and connected to the first interconnect structure. The passivation layer has a spacer portion covering a sidewall of the second dielectric layer and a portion of the first dielectric layer. A ditch exists in the passivation layer and the first dielectric layer. The spacer portion is located between the ditch and the seal ring structure. The semiconductor structure is able to reduce time and power of an etching process for forming the ditch.

Semiconductor structure including seal ring structure

A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.

Metal interconnect structure having cap layer with different thicknesses and method for fabricating the same

An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.

Interconnection structure and manufacturing method thereof

A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.

Semiconductor device including metal interconnections having sidewall spacers thereon, and method for fabricating the same

A method of copper hillock detecting includes the following steps. A testkey structure is disposed on a substrate, wherein the testkey structure includes a lower metallization layer, an upper metallization layer, and a dielectric layer between the lower metallization layer and the upper metallization layer. A force voltage difference is applied to the lower metallization layer and the upper metallization layer under a test temperature and stress time. A changed sensing voltage difference to the lower metallization layer and the upper metallization layer is detected for detecting copper hillock.

Method of copper hillock detecting

A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.

Manufacturing method of connection structure of semiconductor device

A compound control circuit comprises an input end, a light-load signal processing circuit, a slow response circuit and a fast response circuit. The compound control circuit is mainly used as an additional circuit of a work control chip, so that although the work control chip only has a single overcurrent protection level, a compound function control of fast and slow speed, high and low level current protection and light-load signal stabilization can be generated through the compound control circuit, so as to meet the complex application environment and compatible requirements of the current power supply.

Compound control circuit

An optical element including a first substrate, a second substrate, a first optical film, a second optical film, and a spacer is provided. The first optical film is disposed on the first substrate and has a first surface and a plurality of first optical microstructures. The first optical microstructures are disposed on the first surface. The second optical film is disposed on the second substrate and has a second surface and a plurality of second optical microstructures. The second surface is opposite to the first surface. The second optical microstructures are disposed on the second surface. The orthogonal projection of the first optical microstructures on the first substrate does not overlap with the orthogonal projection of the second optical microstructures on the first substrate. The spacer is disposed between the first substrate and the second substrate. A wafer level optical module adopting the optical element is also provided.

Optical element and wafer level optical module

The invention provides an output structure for a power supply, comprising a working circuit board, an output circuit board, a plurality of output connectors, a plurality of heat dissipation plates and a plurality of thermistors. The output circuit board is electrically connected with the working circuit board and is provided with at least one temperature sensing circuit, the plurality of output connectors is arranged on the output circuit board, the plurality of heat dissipation plates is arranged on the output circuit board and close to the output connectors, the plurality of heat dissipation plates senses heat of the output circuit board and at least one of the output connectors at the same time, the plurality of thermistors is arranged corresponding to the plurality of heat dissipation plates one to one and is connected with the at least one temperature sensing circuit.

Output structure for power supply with a plurality of heat dissipation plates

A method for fabricating a metal-insulator-metal (MIM) capacitor is provided. The MIM capacitor includes a substrate, a first metal layer, a deposition structure, a dielectric layer and a second metal layer. The first metal layer is disposed on the substate and has a planarized surface. The deposition structure is disposed on the first metal layer, and at least a portion of the deposition structure extends into the planarized surface, wherein the first metal layer and the deposition structure have the same material. The dielectric layer is disposed on the deposition structure. The second metal layer is disposed on the dielectric layer.

Method for fabricating metal-insulator-metal capacitor

A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.

Method of manufacturing die seal ring

Growing community of inventors

Tainan, Taiwan

Chih-Sheng Chang