Taiwan Semiconductor Manufacturing Comp. Ltd.

Elite Semiconductor Microelectronics Technology Inc.

Au Optronics Corporation

Mosel Vitelic Corporation

Accton Technology Corporation

Chih-Sheng Chang

Cheng-Yi Peng

Ling-Yen Yeh

Yi-Tang Lin

Chia-Cheng Ho

Yee-Chia Yeo

Carlos H Diaz

Tzu-Chiang Chen

Clement Hsingjen Wann

Zhiqiang Wu

Ka-Hing Fung

Chun-Chieh Lu

Kuo-Cheng Ching

Chih Chieh Yeh

Chien-Hsing Lee

Ming-Feng Shieh

Hung-Li Chiang

Chien-Hsun Wang

Chi-Wen Liu

Cheng-Hsien Wu

I-Sheng Chen

Chi-Yuan Shih

Wilman Tsai

Ming-Shiang Lin

Chia-Wen Chang

Chih-Chieh Yeh

Hung-Ming Chen

Tung-Ying Lee

Yu-Lin Yang

Chih-Ping Chao

Meng-Hsuan Hsiao

Hong-Nien Lin

Tsung-Lin Lee

Chien-Wen Chen

Ting-Chu Ko

Cheok-Kei Lei

Chung-Hsien Chen

Chih-Yu Hsu

Hsiao-Hui Chen

Shu-Yu Chen

Isaac Y Chen

Yu-Ning Chang

Sai-Hooi Yeong

Yu-Ming Lin

Bo-Feng Young

Shuo-Mao Chen

Sung-Li Wang

Chee-Wee Liu

Shao-Ming Yu

Sey-Ping Sun

Chi-On Chui

Jyh-Cherng Sheu

Tsu-Hsiu Perng

Jung-Piao Chiu

Ta-Wei Wang

Yin-Pin Wang

Wei-Chun Tsai

Sheng-Ming Huang

Hung-Chih Chang

Hui-Ku Chang

Sheng-Kai Lin

Jeng-Jung Shen

Wei-Chi Wang

Michael Yu

Kuo-Cheng Chiang

Chao-Ching Cheng

Chih-Hao Chang

Shou-Zen Chang

Yu-Chao Lin

Hua-Chou Tseng

Jin Cai

Wei-Jen Lai

Shih-Hsien Huang

Cheng-Tsung Ni

Chung-Ju Chang

Jen-Kuei Lu

Ming-Jui Wang

Wen-Hsien Tu

Jacson Liu

Chun-Hong Chen

Han-Sheng Nian

Ying-Hui Lai

Huai-Chih Ma

CheeWee Liu

Bor-Min Tseng

Hsien-Hui Meng

Yung Chih Tsai

Hudy-Jong Wu

Jiunn-Bin Chen

In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

Semiconductor device and manufacturing method thereof

An integrated circuit die forming method, for forming a plurality of integrated circuit dies on a semiconductor wafer, comprising: forming a first device, a second device in a first die in a first area; forming a metal layer connected to the first device and the second device; forming a third device, a fourth device in a second die in a second area; forming the metal layer connected to the third device and the fourth device, wherein a scribe area exists between the first area and the second area is separated by; wherein the first device and the third device are used for synchronization and are components of a class D amplifier; wherein the second device is used for preventing leakage currents of the first die and the fourth device is used for preventing leakage currents of the second die.

IC die forming method and IC die structure

A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

An electronic device includes a sampling circuit and a summing circuit coupled with the sampling circuit. The sampling circuit samples a pulse width of a first input pulse of a PWM input signal since a first time point on a rising edge of a clock pulse of a clock signal. The summing circuit generates a first output pulse of a PWM output signal since a second time point on a falling edge of the clock pulse. A pulse width of the first output pulse is a summation of the pulse width of the first input pulse and a pulse width of a second input pulse of the PWM input signal, and the second input pulse is the next pulse after the first input pulse.

Electronic device and method for audio signal processing

A semiconductor device includes a ferroelectric field-effect transistor (FeFET), wherein the FeFET includes a substrate; a source region in the substrate; a drain region in the substrate; and a gate structure over the substrate and between the source region and the drain region. The gate structure includes a gate dielectric layer over the substrate; a ferroelectric film over the gate dielectric layer; and a gate electrode over the ferroelectric film.

Analog non-volatile memory device using poly ferrorelectric film with random polarization directions

An electronic device and a method for overcurrent detection are disclosed herein. The electronic device causes a high-side offsetting voltage drop and converts a voltage difference between a first voltage at an input terminal of an upper-bridge power component of a power stage and a sum of a first balancing voltage drop and the high-side offsetting voltage drop into a first current. The electronic device further converts a voltage difference between a second voltage of an output terminal of the upper-bridge power component and a second balancing voltage drop into a second current, compares the first current and the second current, and generates a high-side overcurrent protection (OCP) signal with logic high for a driver of the power stage when the first current is stronger than the second current, such that the driver turns off the upper-bridge power component accordingly.

Electronic device and method for overcurrent detection

A semiconductor structure includes a base layer, a metal-containing gate, a high-k layer and a spacer. The metal-containing gate is disposed over the base layer. The high-k layer is disposed between the base layer and the metal-containing gate. The high-k layer has a protruding portion that protrudes out from a bottom of the metal-containing gate. The spacer is disposed on the sidewall of the metal-containing gate and covers the protruding portion of the high-k layer.

Semiconductor structures and methods of forming the same

The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

Integrated circuit structure and method with solid phase diffusion

A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Semiconductor device

A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

Methods are disclosed herein for forming fin-like field effect transistors (FinFETs) that maximize strain in channel regions of the FinFETs. An exemplary method includes forming a fin having a first width over a substrate. The fin includes a first semiconductor material, a second semiconductor material disposed over the first semiconductor material, and a third semiconductor material disposed over the second semiconductor material. A portion of the second semiconductor material is oxidized, thereby forming a second semiconductor oxide material. The third semiconductor material is trimmed to reduce a width of the third semiconductor material from the first width to a second width. The method further includes forming an isolation feature adjacent to the fin. The method further includes forming a gate structure over a portion of the fin, such that the gate structure is disposed between source/drain regions of the fin.

FinFET device with high-K metal gate stack

An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.

FeFET of 3D structure for capacitance matching

A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.

Semiconductor structure and testing method thereof

Semiconductor device and method for manufacturing the same

A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.

Structure and method for SRAM FinFET device having an oxide feature

Growing community of inventors

Hsinchu, Taiwan

Chih-Sheng Chang