Macronix International Co., Ltd.

Chih-Shen Chang

Kuo-Pin Chang

Hang-Ting Lue

Wen-Wei Yeh

Kuo Pin Chang

Common problems when programming 3D NAND Flash memory having alternating page orientation include the back-pattern effect and pattern-induced program disturb. Improved programming techniques may substantially reduce these problems and, in turn, increase precision when setting memory cells' threshold voltages. Provided are exemplary techniques that combine aspects of 'by-word-line' programming and 'by-page' programming. As such, each page may be programmed beginning with the memory cells that are closest to string select structures, and memory cells on multiple even or odd pages may be programmed substantially simultaneously.

Systems and methods for reduced program disturb for 3D NAND flash

Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors. Provided are exemplary techniques to trim control transistors to provide increased reliability and performance during array operation.

Systems and methods for trimming control transistors for 3D NAND flash

A pre-reading method and a programming method for a 3D NAND flash memory are provided. The pre-reading method comprises the following steps. A selected string includes a first memory cell, two second memory cells and a plurality of third memory cells. The two second memory cells are adjacent to the first memory cell. The third memory cells are not adjacent to the first memory cell. A first pass voltage is applied on the second memory cells, a second pass voltage is applied on the third memory cells, and a read voltage is applied on the first memory cell via a plurality of word lines for reading a data of the first memory cell. The first pass voltage is larger than the second pass voltage.

Pre-reading method and programming method for 3D NAND flash memory

A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting.

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Taipei, Taiwan

Chih-Shen Chang