Vanguard International Semiconductor Corporation

Chicony Electronics Co., Ltd.

Chih-Ping Lin

Shih-Ming Chen

Hsiao-Ying Yang

Pi-Kuang Chuang

Hung-Li Chang

Ya-Sheng Liu

Chung-Yeh Lee

Chih-Feng Chen

Shin-Chin Weng

Po-Sheng Hu

Kuang-Shen Uang

Shih-Yu Hsu

Wen-Hsien Liu

A key includes a substrate, a keycap, a connection component, and protruding structures. The connection component includes a first connection member and a second connection member, and the first connection member and the second connection member are between the substrate and the keycap. The protruding structures are disposed on the upper surface of the first connection member and disposed on the upper surface of the second connection member. When the keycap is pressed to a pressed position, the protruding structures on the first connection member and on the second connection member abut against the bottom surface of the keycap, so that a gap is formed between the keycap and the connection component. Therefore, the bottom surface of the keycap does not contact the upper surface of the first connection member and the upper surface of the second connection member so as to prevent from generating keystroke noises.

A keyboard includes a base plate, a keycap, and at least one balance assembly. The base plate has a plurality of connecting structures. The keycap is above the base plate. The balance assembly includes a balance bar and two silencing members. The balance bar is between the base plate and the keycap and is engaged with the keycap. The silencing members are connected to the balance bar and engaged with the connecting structures. The balance assembly is configured to guide the keycap to move relative to the base plate. Hardnesses of the base plate and the balance bar are greater than a hardness of the silencing members.

Keyboard

A method for forming a semiconductor device structure is provided. The method includes: forming a plurality of trenches in the substrate; forming a gate dielectric layer lining the trenches; filling the trenches with a gate material; etching back the gate material to expose an upper portion of the trenches; forming a first dielectric layer to refill the upper portion of the trenches, and to cover a substrate surface between the trenches; performing a first chemical mechanical planarization process to partially remove the first dielectric layer until the substrate surface between the trenches is exposed. The method also includes using the first dielectric layer in the upper portion of the trenches as an etching mask, etching the substrate through the exposed substrate surface to form a self-aligned contact opening between the trenches.

Method for forming semiconductor device structure

A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.

Semiconductor device

Method for fabricating semiconductor device with increased breakdown voltage

A semiconductor device fabricating method is described. The semiconductor device fabricating method includes providing a substrate. A first gate insulating layer and a second gate insulating layer are formed on the substrate, respectively. A gate layer is blanketly formed. A portion of the gate layer, the first gate insulating layer and the second gate insulating layer are removed to form a first gate, a remaining first gate insulating layer, a second gate and a remaining second gate insulating layer. The remaining first gate insulating layer not covered by the first gate has a first thickness, and the remaining second gate insulating layer not covered by the second gate has a second thickness, wherein a ratio between the first thickness and the second thickness is about 10 to 20. A pair of first spacers and a pair of second spacers are formed on sidewalls of the first gate and the second gate, respectively.

Semiconductor device fabricating method

A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.

Growing community of inventors

Taipei County, Taiwan

Chih-Ping Lin