Powerchip Semiconductor Manufacturing Corporation

Powerchip Technology Corporation

Promos Technologies, Inc

Chih-Ping Chung

Ming-Yu Ho

Saysamone Pittikoun

Hung-Kwei Liao

Jun-Ming Su

Chih-Hao Peng

Ming-Wei Chen

Shih-Ping Lee

Ching-Hung Fu

Wen-Hao Huang

Min-Hui Chen

Chun-Nan Lin

Chung-Yi Chen

Chung-We Pan

Shi-Cheng Lin

Ming-Feng Chang

Jhih Fan Tu

A 3D CMOS image sensor is provided in the present invention, including a semiconductor substrate, a photodiode and a well formed in the semiconductor substrate, a shallow trench isolation (STI) layer formed on a front surface of the semiconductor substrate, a fin protruding upwardly from the semiconductor substrate through the STI layer, wherein the fin is composed of the photodiode and the well, a first gate spanning the photodiode portion and the well portion abutting the photodiode portion of the fin to constitute a transfer transistor, a second gate spanning in the middle of the well portion of the fin to constitute a reset transistor, and a floating diffusion region in the well portion of the fin between the first gate and the second gate electrically connecting the transfer transistor and the reset transistor.

3D CMOS image sensor structure and method of fabricating the same

An image sensor structure including a substrate, a pixel structure, and a deep trench isolation (DTI) structure is provided. The substrate includes a first side and a second side opposite to each other. The pixel structure includes a transfer transistor, a light sensing device, and a floating diffusion region. The transfer transistor includes a first gate. The first gate is disposed on the first side of the substrate. The light sensing device is disposed in the substrate and is located on one side of the first gate. The floating diffusion region is disposed in the substrate and is located on another side of the first gate. The DTI structure extends into the substrate from the second side of the substrate. The top-view pattern of the floating diffusion region does not overlap the top-view pattern of the DTI structure.

Image sensor structure

A back side illumination (BSI) image sensor includes an epitaxial substrate, a deep trench isolation (DTI) structure from one surface to the other surface of the epitaxial substrate, a buried oxide layer on the epitaxial substrate, an epitaxial layer, a well region, a floating diffusion (FD) region, a shallow trench isolation (STI) structure, and vertical transfer gates (VTGs). The buried oxide layer has openings exposing the epitaxial substrate, and the epitaxial layer is formed on the epitaxial substrate and covers the buried oxide layer. The well region is in the epitaxial layer and the epitaxial substrate. The FD region is in the well region above the buried oxide layer, and a width of the buried oxide layer is larger than that of the FD region. The STI structure is in the epitaxial layer. The VTGs are in the epitaxial layer and through the openings of the buried oxide layer.

Back side illumination image sensor and method of manufacturing the same

A backside illuminated image sensor, including a semiconductor layer, a first gate structure, and a light sensing device, is provided. The semiconductor layer has a first surface and a second surface opposite to each other. The first gate structure is disposed on the second surface. The light sensing device is located in the semiconductor layer. The light sensing device extends from the first surface to the second surface.

Backside illuminated image sensor and manufacturing method thereof

Provided are an image sensor and a manufacturing method thereof. In the image sensor, an insulating layer and a first silicon layer are sequentially on a silicon base. A first isolation structure is in the first silicon layer to define an active area (AA). A doped region is in a part of the first silicon layer in the AA and in a part of the silicon base thereunder. A second silicon layer is in a part of the first silicon layer in the AA and extends into the silicon base. An interconnection structure is on the first silicon layer and electrically connected with a transistor. A second isolation structure is in the silicon base under the first isolation structure and connected to the insulating layer. A passivation layer surrounds the silicon base and is connected to the doped region. A microlens is on the silicon base.

Image sensor and manufacturing method thereof

Backside illuminated image sensor and manufacturing method therefore

An image sensor includes a semiconductor substrate, a photodiode formed in the semiconductor substrate, a microlens disposed over the photodiode, a first transfer transistor, a second transfer transistor and a capacitor. The first transfer transistor and the second transfer transistor are formed on the semiconductor substrate, and a memory node is formed in the semiconductor substrate between the first transfer transistor and the second transfer transistor, wherein the first transfer transistor is coupled to the photodiode. The capacitor is formed between the first transfer transistor and the second transfer transistor, and the capacitor includes a first electrode coupled to the memory node, a second electrode on the first electrode and extending to an edge of the photodiode, and a dielectric layer between the first and the second electrodes.

Image sensor and method of manufacturing the same

An image sensor device includes a substrate having a pixel array region, isolation structures in the substrate separating pixel regions from one another in the pixel array region, a photo-sensing region in each of the pixel regions, and a reflective cavity structure in the substrate within each of the pixel region. The reflective cavity structure continuously extends from a bottom of the isolation structure to a deeper central portion of each of the pixel regions, thereby forming a dish-like profile. The reflective cavity structure has a reflective index smaller than that of the substrate.

Image sensor device

A manufacturing method of a non-volatile memory is provided. A tunneling dielectric layer, a first conductive pattern, and isolation structures are formed on a substrate. Using a first photoresist layer as a mask, the first conductive pattern is partially removed to form a first opening exposing the substrate. An insulating layer is formed to fill the first opening and cover the first conductive pattern and the isolation structures. Using a second photoresist layer shielding a portion of the first conductive pattern as a mask, the insulating layer surrounding the first conductive pattern is removed to form a patterned insulating layer having a second opening exposing a portion of the first conductive pattern. An inter-gate dielectric layer and a second conductive pattern are formed on the first conductive pattern to fill the second opening, the first conductive pattern forms a floating gate, and the second conductive pattern forms a control gate.

Non-volatile memory and manufacturing method thereof

A CMOS image sensor unit and a method for fabricating the same are described. The image sensor unit includes a photodiode, a transfer gate, a reset gate, a source follower gate, a floating drain region between the transfer gate and the reset gate, and a PIP capacitor. The lower poly-Si electrode of the PIP capacitor is electrically connected with the floating drain region and the source follower gate to also serve as an interconnect between the floating drain region and the source follower gate. The fabrication method includes forming contact plugs on the floating drain region and the source follower gate, and then forming a PIP capacitor whose lower poly-Si electrode is connected with each contact plug.

CMOS image sensor unit and method for fabricating the same

A manufacturing method of an image sensor is provided. A substrate is provided, and the substrate includes a pixel array region. A plurality of openings is formed in the pixel array region of the substrate. A light guide region is formed in the substrate aside each of the openings, wherein a portion of the substrate is disposed between the light guide region and the opening, and the depth of the light guide region in the substrate is greater than the depth of the opening aside the light guide region in the substrate. Isolation structures are formed in the openings to define a plurality of pixel regions respectively located between two adjacent isolation structures in the pixel array region. A photosensitive region is formed in each of the pixel regions of the substrate. A conductive line layer is formed on each of the pixel regions of the substrate.

A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the sidewall of the shallow trench isolation and is higher than the shallow trench isolation. The tunnel oxide is on the active area. The floating gate is on the tunnel oxide.

Memory structure with high coupling ratio

A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the sidewall of the shallow trench isolation structure, and further comprises a first insulating layer and an L-shape second insulating layer spacer, wherein the first insulating layer is located between the L-shape second insulating layer spacer and the substrate. The tunnel insulating layer is located on the substrate of the active area and connects to the first insulating layer of the composite spacer on its corresponding side.

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Hsinchu, Taiwan

Chih-Ping Chung