Macronix International Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Chih-Ping Chen

Yen-Hao Shih

Yi-Hsuan Hsiao

Chih-Chang Hsieh

Hsu-Shui Liu

Chen-Fu Chien

Chih-Kuo Chang

Yung-Kai Lin

Wei-Ting Hsiao

Shao-Chung Hsu

Kai Lo

Hang-Ting Lue

Ta-Hung Yang

Wei-Chin Lee

Sheng-Chih Lai

Shun-Li Lin

Ming-Hwei Hong

Cheng-Yi Lin

Jueinai Kwo

Chung-Chieh Hsu

Hsin-Cheng Liu

Mao-I Ting

Kuo-Hao Chang

Chian-Kun Chan

Shiang-Pi Chang

Jung-Kuei Lu

Chung-chieh Hsu

De-Chuan Liu

Chian-kun Chan

Yih-Cheng Shih

An apparatus and method for processing semiconductor substrates provides a substrate stage being a rotatable disc with a solid surface and a terraced edge with upper, intermediate and lower portions of increasing diameter. A hollow edge ring rests on the intermediate edge portion and a substrate disposed on the rotatable disc is lifted and transported by robot blades positioned beneath the edge ring and which lift the edge ring which holds the substrate around its edges. The rotatable disc and edge ring find application in MOCVD and other semiconductor manufacturing tools.

Semiconductor apparatus with transportable edge ring for substrate transport

A plurality of semiconductor layers is etched to define a first plurality of stacks of active strips between a first plurality of trenches. A first memory layer is formed on side surfaces of active strips in the first plurality of trenches, and a first layer of conductive material is formed over the first memory layer. The first plurality of stacks is etched to define a second plurality of stacks of active strips between a second plurality of trenches of the plurality of semiconductor layers. A second memory layer is formed on side surfaces of active strips in the second plurality of trenches, and a second layer of conductive material is formed over the second memory layer. Channel regions of memory cells in the memory device are formed in active strips of the plurality of semiconductor layers in the second plurality of stacks.

High aspect ratio etching method

A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.

Conductor structure and method

A memory device includes an array of dielectric charge trapping structures memory cells including word lines and bit lines. Control circuitry is coupled to the array arranged to control read, program and erase operations. A controller is arranged with supporting circuitry thermally annealing charge trapping structures in the memory cells in the array. Word line drivers and word line termination circuits can be used to induce current flow on the word lines to induce heat for the annealing. The thermal annealing can be applied interleaved with normal operations for recover from cycling damage. Also, the thermally annealing can be applied during mission functions like erase, to improve performance of the function.

Thermally assisted dielectric charge trapping flash

A method for forming a semiconductor device includes placing a Si substrate and an ScOpowder source in an oxide chamber, and vaporizing the ScOpowder source in the oxide chamber so as to form a single crystal ScOfilm on the Si substrate through electron beam evaporation techniques.

Method for forming a semiconductor device having a structure of a single crystal scandium oxide film formed on a silicon substrate

In the manufacturing of VLSI circuits, production of overlay is a critical step. To obtain a higher resolution and alignment accuracy in microlithographic process, overlay errors must be measured so that overlay errors can be reduced to a tolerable level. This invention provides an overlay error model and a sampling strategy. Utilizing the overlay model and sampling strategy, a device for measuring overlay errors is also designed.

Overlay error model, sampling strategy and associated equipment for implementation

The current invention provides a method for analyzing process variations that occur during integrated circuit fabrication. Critical dimension data is collected for each layer of the integrated circuit fabrication process for a period of time and a shift indicator that indicates variation in the critical dimension data for each layer of the integrated circuit fabrication process is calculated. A machine drift significance indicator is also calculated for each machine used in each layer of the integrated circuit fabrication process, and a maximum shift of mean value for each layer of the integrated circuit fabrication process is defined. The shift indicator, the maximum shift of mean value and the machine drift significance indicator are used to determine at least one likely cause of variation in critical dimension for each layer of the integrated circuit fabrication process.

Critical dimension statistical process control in semiconductor fabrication

A method of fabricating a read only memory. After forming bit lines and word lines in a substrate, a coding process is performed. A photoresist layer is formed on the substrate while performing the coding process. The photoresist layer covering a part of a first channel region under the word line is exposed, and then the photoresist layer covering a part of a second channel region under the word lines is exposed. A development step is performed to remove the photoresist layer that has been exposed. Using the remaining photoresist layer as a mask to perform an ion implantation, a coding area is formed in the first channel region and the second channel region. The photoresist layer is removed.

Method of fabricating read only memory

Conventionally, efforts to improve the yield of chips produced on a wafer focused on defect reduction. Another approach is optimizing wafer exposure patterns. The present invention includes a computer-based procedure and apparatus to expose cells on the surface of a wafer so as to maximize the number of dies produced from a wafer. The invention is useful in the exposure of six and eight inch wafers, as well as larger wafers.

Procedure of alignment for optimal wafer exposure pattern

Growing community of inventors

Hsinchu, Taiwan

Chih-Ping Chen