Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Ping Chao

Chung-Long Chang

Chun-Hung Chen

Kuan-Chi Tsai

Wei-Kung Tsai

Hua-Chou Tseng

Kuo-Yu Cheng

Der-Chyang Yeh

Harry-Hak-Lay Chuang

Alexander Kalnitsky

Tsung-Yu Yang

Jye-Yen Cheng

Chih-Sheng Chang

Chia-Yi Chen

Chun-Hong Chen

Chia-Shiung Tsai

Shuo-Mao Chen

Ru-Liang Lee

Szu-Yu Wang

Shih-Shiung Chen

Kuan-Liang Liu

Eugene I-Chun Chen

Keng-Yu Chen

Chewn-Pu Jou

Yung-Chow Peng

Chung-Yi Yu

Fu-Lung Hsueh

Ming Chyi Liu

Hsun-Chung Kuang

Hsing-Kuo Hsia

Hsi-Kuei Cheng

Alex Kalnitsky

Ching-Chung Hsu

Sung-Hsiung Wang

Chien-Chih Ho

Wei-Chun Hua

Yi-Sin Wang

Chin-Hao Su

Shao-Yu Chen

Kuo-Tung Sung

Chen-Yao Tang

Chia-Yi Su

Hao-Hsun Lin

Yueh-You Chen

Michael Yu

Hsiang-Chi Chen

Yu Hung Chen

Cheng-Chang Hsu

Chi-Feng Huang

Yuan-Tai Tseng

Jui-Feng Kuan

Chih-Hsien Lin

Shih-Hsien Yang

Heng-Ming Hsu

John Chern

Li-Wen Chang

Ping Chun Yeh

Meng-Wei Hsieh

Li-Weng Chang

Kuan-liang Liu

Yung-chih Tsai

Chun-hung Chen

Shaoqiang Zhang

Chun-pei Wu

Shu-Jenn Yu

Hua-Chao Tseng

Chia-Yu Su

Yung Chih Tsai

Chun Chieh Wu

The present disclosure relates to an integrated chip. The integrated chip includes an epitaxial layer arranged on a semiconductor body. A trap-rich layer is arranged on the epitaxial layer, a dielectric layer is arranged on the trap-rich layer, and an active semiconductor layer is arranged on the dielectric layer. A semiconductor material is arranged on the epitaxial layer and laterally beside the active semiconductor layer. The epitaxial layer continuously extends from directly below the trap-rich layer to directly below the semiconductor material.

Multi-function substrate

A method includes: receiving a composite substrate including a first region and a second region, the composite substrate comprising a semiconductor substrate and an insulator layer over the semiconductor substrate; bonding a silicon layer to the composite substrate; depositing a capping layer over the silicon layer; forming a trench through the capping layer, the silicon layer and the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench; removing the capping layer to form an epitaxial layer from the silicon layer and the initial epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.

Semiconductor structure and manufacturing method thereof

The present disclosure relates to an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

The present disclosure relates an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.

Integrated circuit

Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

Trap layer substrate stacking technique to improve performance for RF devices

An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Integrated circuit and manufacturing method thereof

A method of forming a capacitor structure includes forming a first set of electrodes having a first electrode and a second electrode, wherein each electrode of the first set of electrodes has an L-shaped portion. The method further includes forming a second set of electrodes having a third electrode and a fourth electrode, wherein each electrode of the second set of electrodes has an L-shaped portion. The method further includes forming insulation layers between the first set of electrodes and the second set of electrodes. The method further includes forming a first L-shaped line plug connecting the first electrode to the third electrode, wherein an entirety of an outer surface of the first L-shaped line plug is recessed with respect to an outer surface of the L-shaped portion of the first electrode. The method further includes forming a second line plug connecting the second electrode to the fourth electrode.

Method of forming capacitor structure

Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer.

Semiconductor device and method for forming the same

An integrated circuit includes a substrate, a first inter-layer dielectric (ILD) layer over the substrate, and a gate strip having a first width formed in the first ILD layer. A conductive strip having a second width is provided on the gate strip, with the second width being greater than the first width. The conductive strip is positioned so that the gate strip is covered and a portion of the conductive strip extends over a top surface of the first ILD adjacent the gate strip. A second ILD layer is provided over the conductive strip and the first ILD layer with a contact plug extending through the second ILD layer to provide electrical contact to the conductive strip.

Metal gate transistor, integrated circuits, systems, and fabrication methods thereof

A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.

A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.

Cascode CMOS structure

A method for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an interface layer is formed between the substrate and the buried oxide layer. The method also includes etching through the buried oxide layer and the interface layer to form a deep trench, and a bottom surface of the deep trench is level with a bottom surface of the interface layer. The method further includes forming an implant region directly below the deep trench and forming an interlayer dielectric layer in the deep trench.

Mechanisms for forming radio frequency (RF) area of integrated circuit structure

Growing community of inventors

Hsin-Chu, Taiwan

Chih-Ping Chao