Advanced Semiconductor Engineering, Inc.

Advanced Semiconductor Engineering, Inc. Kaohsiung, Taiwan

Chih-Pin Hung

Chi-Tsung Chiu

Ian Hu

Tang-Yuan Chen

Meng-Kai Shih

Dao-Long Chen

Teck-Chong Lee

Chen-Chao Wang

William T Chen

John Richard Hunt

Shin-Luh Tarng

Ying-Ta Chiu

Mei-Ju Lu

Kuo-Hsien Liao

Chi-Han Chen

Chih-Yi Huang

Jr-Wei Lin

Ying-Te Ou

Chang-Yu Lin

Ping-Feng Yang

In-De Ou

Ming-Hung Chen

Chin-Li Kao

Pao-Nan Lee

Chang Chi Lee

Sheng-Chi Hsieh

Jin-Feng Yang

Cheng-Yu Ho

Chien Lin Chang Chien

Yong-Da Chiu

Jui-Cheng Huang

Chih-Cheng Lee

Jian-Cheng Chen

Meng-Wei Hsieh

Yung-Chi Lee

Yung-Shun Chang

Shin-Hua Chao

Yung-Hui Wang

Chin-Cheng Kuo

Ming-Han Wang

Sung-Mao Wu

Hsin-En Chen

Jin-Yuan Lai

Kwang-Lung Lin

Tse-Chuan Chou

Chen-Chuan Fan

Tsun-Lung Hsieh

Ying-Xu Lu

Chih-Wei Tsai

Shang-Kun Huang

Juang-Sheng Chiang

Jung-Che Tsai

Shiu-Chih Wang

Chi-Hung Pan

Chia-Shang Chen

Kuang-Hua Lin

Bau-Nan Lee

Cheng-Fen Chen

Jia-Rung Ho

Jung-sheng Chiang

Po-Hsien Ke

An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

Electronic device package and method for manufacturing the same

A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

Semiconductor device packages and methods of manufacturing the same

An electronic device is provided. The electronic device includes an antenna array including a plurality of antenna patterns collectively configured to provide a scan-angle coverage. Each of the antenna patterns includes a curved surface.

Electronic device

A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.

Package structure and method for manufacturing the same

The present disclosure relates to a wireless communication module. The wireless communication module includes a first antenna layer and a second antenna layer non-coplanar with the second antenna layer. An electromagnetic wave of the first antenna and the second antenna are configured to have far-field interference to each other.

Semiconductor device package and method of manufacturing the same

An assembly structure and a method for manufacturing an assembly structure are provided. The assembly structure includes a wiring structure and a semiconductor element. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the at least one dielectric layer, and defines an accommodating recess recessed from a top surface of the wiring structure. The wiring structure has a smooth surface extending from the top surface of the wiring structure to a surface of the accommodating recess. The semiconductor element is disposed in the accommodating recess.

Assembly structure and method for manufacturing the same

A wiring structure is provided. The wiring structure includes an upper redistribution structure, a lower redistribution structure, a conductive structure, an upper bonding layer and a lower bonding layer. The conductive structure is disposed between and electrically connected to the upper redistribution structure and the lower redistribution structure. The upper bonding layer is disposed between the upper redistribution structure and the conductive structure to bond the upper redistribution structure and the conductive structure together. The lower bonding layer is disposed between the lower redistribution structure and the conductive structure to bond the lower redistribution structure and the conductive structure together.

Wiring structure

A semiconductor device package includes a substrate, an electronic component disposed on the substrate, a supporting structure disposed on the substrate and surrounding the electronic component, and a heat spreading structure disposed on the supporting structure. A length of the supporting structure and a length of the heat spreading structure are greater than a length of the substrate.

An electronic device includes a main substrate, a semiconductor package structure and at least one heat pipe. The semiconductor package structure is electrically connected to the main substrate, and includes a die mounting portion, a semiconductor die and a cover structure. The semiconductor die is disposed on the die mounting portion. The cover structure covers the semiconductor die. The heat pipe contacts the cover structure for dissipating a heat generated by the semiconductor die.

Electronic device comprising heat pipe contacting a cover structure for heat dissipation

A semiconductor package structure includes a package substrate, at least one semiconductor die, a heat dissipating device, at least one electronic device and a heat transmitting structure. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is electrically connected to the first surface of the package substrate. The heat dissipating device is thermally connected to the first surface of the package substrate. The electronic device is electrically connected to the second surface of the package substrate. The electronic device has a first surface and a second surface opposite to the first surface, and the first surface of the electronic device faces the second surface of the package substrate. The heat transmitting structure is disposed adjacent to the second surface of the package substrate, and thermally connected to the electronic device and the heat dissipating device.

Substrate structure and semiconductor package structure

A semiconductor package includes a substrate, a semiconductor chip and a heat dissipation structure. The semiconductor chip includes a first surface, a second surface opposite to the first surface, and at least one chip pad disposed adjacent to the first surface. The chip pad is electrically connected to the substrate. The heat dissipation structure is disposed adjacent to the second surface of the semiconductor chip and a portion of the substrate. An area of the heat dissipation structure is greater than an area of the semiconductor chip.

Semiconductor package

Growing community of inventors

Kaohsiung, Taiwan

Chih-Pin Hung