United Microelectronics Corp.

United Microelectronics Corps.

Chih-Ning Wu

Chan-Lon Yang

Chung-Ju Lee

Kuan-Yang Liao

Sun-Chieh Chien

Wei-Tsun Shiau

Charlie C J Lee

Po-Chao Tsao

Ming-Tsung Chen

Yu-Lan Chang

Chang-Chi Huang

Yi-Yiing Chiang

Cheng-Yuan Tsai

Hsiao-Pang Chou

Pei-Jen Wang

Jain-Hon Chen

Ming-Hsing Liu

Cheng-Kuen Chen

Hsin Tai

Wen-Liang Lien

Ching-Piao Lin

Wen-Fu Yu

A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

Fabricating method for a metal oxide semiconductor transistor

A method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process is disclosed, in which the gate electrode, a metal silicide layer, a spacer, a silicon nitride cap layer, and a dielectric layer have been formed. The method includes performing a chemical mechanical polishing process to polish the dielectric layer using the silicon nitride cap layer as a polishing stop layer to expose the silicon nitride cap layer over the gate electrode; removing the exposed silicon nitride cap layer to expose the metal silicide layer; and performing a first etching process to remove the metal silicide layer on the gate electrode.

Method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process and etching method

A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate contains a gate structure thereon; performing an etching process to form two recesses corresponding to the gate structure within the semiconductor substrate; performing an oxygen flush on the semiconductor substrate; performing a cleaning process on the semiconductor substrate; and performing a selective epitaxial growth (SEG) to form an epitaxial layer in each recess for forming a source/drain region.

Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors

A method of fabricating a semiconductor device is disclosed. The method includes defining an electrode on a semiconductor substrate; forming a spacer on at least one sidewall of the electrode; performing a process operation on the semiconductor substrate using the spacer as a mask and forming a material layer on the top or the surface of the semiconductor substrate and the electrode; and removing the spacer by steps of performing a wet etching process at a temperature in a range of 100&#xb0; C. to 150&#xb0; C. to etch the spacer using an acid solution containing phosphoric acid as an etchant. With respect to another aspect, a method of removing a spacer is also disclosed. The method includes performing a wet etching process at a temperature in a range of 100&#xb0; C. to 150&#xb0; C. to etch the spacer using an acid solution containing phosphoric acid as an etchant.

Method of fabricating semiconductor devices and method of removing a spacer

A method of cleaning a wafer, adapted for a patterned gate structure. The gate structures comprise a gate dielectric layer, a nitrogen-containing barrier layer and a silicon-containing gate layer sequentially stacked over the substrate. The method includes cleaning the substrate with phosphoric acid solution and hydrofluoric acid solution so that silicon nitride residues formed in a reaction between the nitrogen-containing barrier layer and the silicon-containing gate layer can be removed and the amount of pollutants and particles can be reduced. Ultimately, the yield of the process as well as the quality and reliability of the device are improved.

Method of cleaning wafer and method of manufacturing gate structure

Metal oxide semiconductor transistor

A method of removing spacers after forming a MOS transistor on a wafer. The MOS transistor comprises a gate disposed on the substrate, spacers disposed on the sidewalls of the gate and a source and a drain region in the substrate beside the spacers. The spacers are removed by performing a wet etching process in the dark such that during the spacer removal process, the source and the drain region in a MOS transistor can be prevented from damages.

Method of removing spacers and fabricating MOS transistor

An extrusion-free wet cleaning process for post-etch Cu-dual damascene structures is developed. The process includes the following steps: (1). providing a wafer having a silicon substrate and at least one post-etch Cu-dual damascene structure, the post-etch Cu-dual damascene structure having a via structure exposing a portion of a Cu wiring line electrically connected with an Ndiffusion region of the silicon substrate, and a trench structure formed on the via structure; (2). applying a diluted HOsolution on the wafer to slightly oxidize the surface of the exposed Cu wiring line; (3). washing away cupric oxide generated in the oxidation step by means of an acidic cupric oxide cleaning solution containing diluted HF, NHF or NHOH; and (4). providing means for preventing Cu reduction reactions on the Cu wiring line.

Extrusion-free wet cleaning process for copper-dual damascene structures

A method for avoiding resist poisoning during a damascene process is disclosed. A semiconductor substrate is provided with a low-k dielectric layer (k&#x2266;2.9) thereon, a SiC layer over the low-k dielectric layer, and a blocking layer over the SiC layer. The blocking layer is used to prevent unpolymerized precursors diffused out from the low-k dielectric layer from contacting an overlying resist. A bottom anti-reflection coating (BARC) layer is formed on the blocking layer. A resist layer is formed on the BARC layer, the resist layer having an opening to expose a portion of the BARC layer. A damascene structure is formed in the low-k dielectric layer by etching the BARC layer, the blocking layer, the SiC layer, and the low-k dielectric layer through the opening.

Damascene process capable of avoiding via resist poisoning

An extrusion-free wet cleaning process for post-etch Cu-dual damascene structures is developed. The process includes the following steps: (1). providing a wafer having a silicon substrate and at least one post-etch Cu-dual damascene structure, the post-etch Cu-dual damascene structure having a via structure exposing a portion of a Cu wiring line electrically connected with an N diffusion region of the silicon substrate, and a trench structure formed on the via structure; (2). applying a diluted H O solution on the wafer to slightly oxidize the surface of the exposed Cu wiring line; (3). washing away cupric oxide generated in the oxidation step by means of an acidic cupric oxide cleaning solution containing diluted HF, NH F or NH OH; and (4). providing means for preventing Cu reduction reactions on the Cu wiring line.

The present invention pertains to a via-first dual damascene process. A semiconductor substrate having a conductive structure and a dielectric layer on the semiconductor substrate is provided. The dielectric layer has a via opening exposing the conductive structure. The via opening is filled with a gap-filling polymer to form a gap-filling polymer (GFP) layer on the dielectric layer. The GFP layer is etched back to a predetermined depth such that an exposed surface of the GFP layer is lower than surface of the dielectric layer to form a recess, thereby exposing portions of sidewalls of the via opening. A surface treatment for altering surface property of the sidewalls and the exposed surface of the GFP layer is then carried out, thereby preventing a subsequent deep UV photoresist from interacting with the sidewalls or the exposed surface of the GFP layer either in a chemical or physical way.

Via-first dual damascene process

First of all, a breakthrough process is performed for removing the polymer and oxidized residues remained on top surface of the hard-mask layers, wherein the breakthrough process utilizes a CF -based mixed-gas, such as Ar/O /CF , to slightly flush out the top surface of the hard-mask layers so as to strip the polymer and oxidized residues remained thereon. Afterward, an etching process is performed to etch through the hard-mask layers until a predetermined thickness of the dielectric layer. Finally, another etching process is performed to etch through the hard-mask layer and the dielectric layer and form the damascene structure in the dielectric layer, wherein this etching process utilizes the mixed gas having chlorine, such as O /Cl .

Etching process for forming damascene structure of the semiconductor

A method is provided for cleaning a dual damascene structure. A first metal layer, a cap layer, and a dielectric layer are formed on a substrate in sequence. Then a dual damascene opening is formed in the dielectric layer and the cap layer exposing the first metal layer. Next, a post-etching cleaning step is carried out to clean the dual damascene opening using a fluorine-based solvent. Then, an argon gas plasma is sputtered to clean the dual damascene opening before a second metal layer fills in the dual damascene opening.

Method of cleaning a dual damascene structure

A method of cleaning a dual damascene structure. A first metal layer, a cap layer, and a dielectric layer are formed on a substrate in sequence. Then a dual damascene opening is formed in the dielectric layer and the cap layer, exposing the first metal layer. Then, a post-etching cleaning step is carried out to clean the dual damascene opening, and there are two types of cleaning methods. The first method uses a fluorine-based solvent to clean the dual damascene opening. An alternative cleaning method uses a hydrogen peroxide based solvent at a high temperature, followed by a hydrofluoric acid solvent cleaning step. Then, an argon gas plasma is sputtered to clean the dual damascene opening before a second metal layer fills in the dual damascene opening.

A method of cleaning a dual damascene structure includes forming a first conductive layer in a substrate. A dielectric layer is formed over the substrate. A dual damascene opening is formed in the dielectric layer to expose the first conductive layer. A H O based aqueous solution is used to remove polymer residues in the dual damascene opening. A temperature of the H O based aqueous solution is controlled so that the first conductive layer is not corroded. A diluted HF solution or a diluted HF and HCl solution is used to remove the polymer residues. A second conductive layer is formed over the substrate to fill the dual damascene opening. A chemical mechanical polishing process is performed with the dielectric layer serving as a polishing stop to remove the second conductive layer outside the dual damascene opening. A H O based aqueous solution is used to clean the hydrocarbon particulates from the chemical mechanically polishing step. A diluted HF solution or a diluted HF and HCl solution is used to remove the slurry residues, such as silicon oxide of the slurry, from the chemical mechanical polishing step.

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Hsin-Chu, Taiwan

Chih-Ning Wu