Storart Technology Co., Ltd.

Skymedi Corporation

Chih Nan Yen

Jui Hui Hung

Fuja Shone

Yung Li Ji

Chien Lin

Fu-Ja Shone

Yung-Li Ji

Shih Chieh Tai

Szu I Yeh

Hsin Jen Huang

Chia Chen Chang

Hsueh Chih Yang

Yu Mao Kao

Chia Hao Lee

A method for encoding multi-modes of BCH codes and an associated encoder is disclosed. The method has the steps of: building a number of encoding matrices; combining the encoding matrices with one side aligned to form a combined matrix; seeking common sub-expressions (CSEs) in the combined matrix, and encoding a message using the combined matrix.

Method for encoding multi-mode of BCH codes and encoder thereof

A method and decoder for early terminating decoding processes of serial concatenated coding are disclosed. The method includes the steps of providing a codeword, encoded by a first coding and a second coding sequentially; setting a maximum syndrome weight; decoding the second coding for the codeword by iterative calculations for syndromes; terminating decoding of the second coding if a number of the iterative calculations reaches a preset number or a syndrome weight of one iterative calculation is equal to or smaller than the maximum syndrome weight, otherwise repeating the decoding step and the terminating step; and decoding the first coding for the codeword.

Method for early terminating decoding processes of serial concatenated coding and decoder using the same

The present invention discloses a multi-code Chien's search circuit for BCH codes with various values of m in GF(2). The circuit includes: a combined matrix unit, a number of first multiplexers, a number of registers and a number of second multiplexers. By designing the Chien's search circuit having several Chien's search matrices, with peripheral components, it is able to achieve applications for different code rates, different code lengths and even different m in GF(2).

[object Object]

A simplified inversionless Berlekamp-Massey algorithm for binary BCH codes and circuit implementing the method are disclosed. The circuit includes a first register group, a second register group, a control element, an input element and a processing element. By breaking the completeness of math structure of the existing simplified inversionless Berlekamp-Massey algorithm, the amount of registers used can be reduced by two compared with conventional algorithm. Hardware complexity and operation time can be reduced.

Simplified inversionless berlekamp-massey algorithm for binary BCH code and circuit implementing therefor

A serial multiply accumulator (MAC) for operation of two multiplications and one addition over Galois field is disclosed. The MAC includes a first element feeding circuit, a second element feeding circuit, a number of first calculating circuits and a second calculating circuit. By re-arranging the circuit design, many elements used in the conventional MAC, such as XOR gates and registers, can be saved. The present invention has an advantage of lower area cost.

Serial multiply accumulator for galois field

A data format with ECC information for on-the-fly decoding during data transfer and method for forming the data format are disclosed. The method includes the steps of: dividing a parity check matrix having a message segment and a parity segment into a plurality of layers; choosing parity bit nodes in the parity segment of a first layer connected to check nodes; assembling the chosen parity bit nodes as a first parity segment and the rest parity bit nodes as a second parity segment; reallocating the parity check matrix so that the first parity segment is on the head of the message segment and the second parity segment is on the end of the message segment; forming a generating matrix according to the reallocated parity check matrix; and operating a message with the generating matrix to obtain the codeword.

Data format with ECC information for on-the-fly decoding during data transfer and method for forming the data format

An encoding and syndrome computing co-design circuit for BCH code and a method for deciding the circuit are disclosed. The method includes the steps of: building up matrices of X, Xand Xaccording to p parallel computations and 2t syndromes; building up F; building up F'; building up F&#x2033;; building up matrix of [XF&#x2033;]; and designing a circuit which fulfills the operation of [XF&#x2033;].

Encoding and syndrome computing co-design circuit for BCH code and method for deciding the same

A method for shortening latency of Chien's search and related circuit are disclosed. The method includes the steps of: determining a shifted factor, p; receiving a BCH codeword; computing a syndrome from the BCH codeword; finding an error-location polynomial based on the syndrome; and processing Chien's search for the error-location polynomial to find out roots thereof. p is a number of successive zeroes from the first bit of the BCH codeword, the Chien's search starts iterative calculations by substituting a variable of the error-location polynomial with a nonzero element in Galois Field, GF(2), and the nonzero element ranges from &#x3b1;to &#x3b1;, wherein n is a codelength of the BCH codeword and equals 2&#x2212;1, and m is a positive integer.

Method and circuit for shortening latency of Chien'S search algorithm for BCH codewords

An operation method of a memory includes the steps of calculating an offset of sequential write commands and the beginning of pages of a block of a non-volatile memory; shifting the block by the offset; and directly writing data from a host to the pages except the first and last pages of the block by the sequential write commands. In an embodiment, the pages are logical pages providing optimal writing efficiency and are determined before calculating the offset. The step of shifting the block by the offset is to increase corresponding logical block addresses (LBA) in the pages by the offset.

Method for sequentially writing data with an offset to a non-volatile memory

A method of wear leveling for a non-volatile memory is disclosed. A non-volatile memory is divided into windows and gaps, with each gap between two adjacent windows. The windows comprise physical blocks mapped to logical addresses, and the gaps comprise physical blocks not mapped to logical addresses. The windows are shifted through the non-volatile memory in which the mapping to the physical blocks in the window to be shifted is changed to the physical blocks in the gap.

Method of wear leveling for non-volatile memory and apparatus using via shifting windows

A non-volatile memory device, and a method for accessing the non-volatile memory device are provided. The non-volatile memory device is connected to a host via a bus. The non-volatile memory device comprises an MCU. By independently processing the particular commands using only the auxiliary circuit, the MCU can cease to operate, thus saving power. By setting the bus into power saving mode when the non-volatile memory device is busy, the host and the non-volatile memory device would not communicate mutually, thus, saving power.

Non-volatile memory device, and method of accessing a non-volatile memory device

A method for managing defect blocks in a non-volatile memory essentially comprises the steps of detecting defect blocks in the non-volatile memory, storing addresses of the defect blocks in a table block of the non-volatile memory, and setting the non-volatile memory to be read-only if the quantity of defect blocks in the non-volatile memory exceeds a threshold and no free blocks remain in the non-volatile memory. In a preferred embodiment, the free pages in the defect block continue to be programmed before setting the non-volatile memory to be read-only.

Growing community of inventors

Hsinchu, Taiwan

Chih Nan Yen