Global Unichip Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Chih-Mou Tseng

Min-Hsiu Tsai

Ming-Tung Chang

Chien-Mo Li

Cheng-Hong Tsai

Yih-Chih Chou

Jen-Yang Wen

A computer executing method is provided in this disclosure. The computer executing method is configured for synthesizing a clock tree circuit, the clock tree circuit includes a plurality of clock pins, a plurality of weight values are set between any of the clock pins, the computer executing method includes steps of: establishing a graph model; utilizing a force directed algorithm to calculate a branch position according to the weight values and a position of the clock pins; setting a guide buffer in the branch position and updating a netlist; performing a clock tree synthesis (CTS) and executing a post-CTS static timing analysis (STA); determining whether an analysis result of the post-CTS STA and a timing setup value is identical or not; and if the analysis result does not match the timing setup value, re-establishing a graph model.

Computer executing method, clock data processing system and computer readable storage medium

A through-silicon via (TSV) testing structure is disclosed herein and includes a plurality of controllers, a plurality of transmitters and a plurality of receivers. The controllers are configured to output a first controlling signal and a second controlling signal. The transmitters are respectively connected to the output end of the through-silicon via and one of the controllers, and output a testing output signal in accordance with the first controlling signal and the second controlling signal. The receivers are respectively connected to the input end of the through-silicon via and another one of the controllers, and input a testing input signal in accordance with the first controlling signal and the second controlling signal.

Through silicon via testing structure

In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan cells, the first scan cells are arranged to be on a first scan chain, and the second scan cells are arranged to be on a second scan chain. The method includes: for a first region in the layout, determining whether the first region needs a test clock domain adjustment according to densities of first scan cells and second scan cells within the first region; and when it is determined that the first region needs the test clock domain adjustment, arranging at least one first scan cell within the first region to be on the second scan chain.

Method for creating test clock domain during integrated circuit design, and associated computer readable medium

Growing community of inventors

Chiayi County, Taiwan

Chih-Mou Tseng