Industrial Technology Research Institute

Adeia Semiconductor Bonding Technologies Inc.

Win-house Electronic Co., Ltd.

Chih-Ming Tzeng

Yu-Hua Chen

Shou-Lung Chen

Jyh-Rong Lin

Shan-Pu Yu

Jeng-Dar Ko

Ching-Wen Hsiao

Chih-Ming Shen

Ching-Wen Hsaio

Chun-Kai Liu

Tao-Chih Chang

Ming-Ji Dai

Yu-Lin Chao

Chih-Chung Chiu

Jing-Yao Chang

Kuo-Shu Kao

Fang-Jun Leu

Ming-Kaan Liang

Hsin-Han Lin

Li-Ling Liao

Hsiao-Ming Chang

Shian-Chiau Chiou

Yu-Hua Cheng

A power integrated module (PIM) and a motor control system are provided. The PIM is adapted to drive a motor. The PIM includes a first transformation circuit, a second transformation circuit, and a plurality of shunt units. The first transformation circuit includes a plurality of first half-bridge circuits, and a coupling relationship among the first half-bridge circuits is selected, so that the first transformation circuit is operated in a rectifier mode or an inverter mode. The second transformation circuit includes a plurality of second half-bridge circuits coupled to the motor. The shunt units are respectively coupled between the second half-bridge circuits and the motor and configured to sense a current between the second transformation circuit and the motor.

Power integrated module and motor control system

A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.

Semiconductor package structure

An intelligent diagnosis system for a power module. The system includes a power module, a hardware checking module and a diagnostic module. The power module has a temperature sensing element for obtaining a temperature difference between a starting minimum temperature and a current temperature. The hardware checking module has a current sensing element, a voltage sensing element and a magnetic coupling closed loop detection element for obtaining the current, the output voltage and the input voltage of the power module, and the hardware loop status, respectively. The diagnostic module calculates the number of cycles that have been operated, a measured impedance and an instantaneous power based on those measurement results, and calculating a risk index based on the number of cycles that have been operated, the temperature difference, the measured impedance, the instantaneous power and the hardware loop status, thereby determining the accumulation of the abnormality index record.

Intelligent diagnosis system for power module and method thereof

A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Electrically stackable semiconductor wafer and chip packages

Wafer leveled chip packaging structure and method thereof

Wafer-leveled chip packaging structure and method thereof

This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Semiconductor package device

Growing community of inventors

Fengshan, Taiwan

Chih-Ming Tzeng