Taiwan Semiconductor Manufacturing Comp. Ltd.

Foxsemicon Integrated Technology, Inc.

Industrial Technology Research Institute

Tsinghua University

Comp-any Gmbh

Chih-Ming Lai

Ru-Gun Liu

Jiann-Tyng Tzeng

Chih-Liang Chen

Charles Chew-Yuen Young

Kam-Tou Sio

Shih-Ming Chang

Ken-Hsien Hsieh

Ming-Young Shiao

Hong-Bin Yang

Shih-Wei Peng

Tsai-Sheng Gau

Ming-Feng Shieh

Wei-Cheng Lin

Chun-Kuang Chen

Wei-Liang Lin

Yung-Sung Yen

Wen-Chun Huang

Hui-Ting Yang

Lei-Chun Chou

Chin-Yuan Tseng

An-Chi Wei

Cheng-Chi Chuang

Yi-Hsiung Lin

Tsong-Hua Ou

Chin-Hsiang Lin

Jyh-Long Chern

Chien-Wen Lai

Yao-Ching Ku

Shau-Lin Shue

Chung-Ju Lee

Tien-I Bao

Chia-Tien Wu

Shun Li Chen

Jyu-Horng Shieh

Yu-Xuan Huang

Chia-Ying Lee

Yung-Hui Yeh

Hui-Zhong Zhuang

Ting-Wei Chiang

Yi-Kan Cheng

Wen-Hao Chen

Jung-Chan Yang

Guo-Huei Wu

Chi-Yeh Yu

Yu-Jung Chang

Ying-Chou Cheng

Pochun Wang

Wen-Li Cheng

Cliff Hou

Chi-Chang Liao

Meng-Hung Shen

Ko-Bin Kao

Shi Ning Ju

Tien-Lu Lin

Po-Chun Liu

Wei-Hao Wu

Cheng-Hsiung Tsai

Yen-Chun Huang

Ching-Wei Tsai

Chia-Hao Chang

Pin-Dai Sue

Ya Hui Chang

Hsin-Chih Chen

Yung-Chin Hou

Hsiao-Shu Chao

Wen-Jang Jiang

Shih-Chun Huang

Yu-Pin Liu

Yu-Chen Chang

Kuo-Cheng Ching

Kuo-Cheng Chiang

Lee-Chung Lu

Chi-Cheng Hung

Wen-Yung Yeh

Hsin-Ping Chen

Wei-An Lai

Chien-Hsun Chen

Hsu-Ting Huang

Hung-Kuang Hsu

Yen-Ming Chen

Li-Te S Lin

Dian-Hau Chen

Huan-Just Lin

Burn Jeng Lin

Yuan-Te Hou

Yi-Hsun Chiu

Hung-Chang Hsieh

Shang-Wen Chang

Kuei Shun Chen

Chii-Ping Chen

Chun-Ting Liu

Cheng-I Huang

Gwan Sin Chang

Yu-Tien Shen

Ming-Hui Chih

Tsung-Yao Wen

Hsi-Hsuan Yen

Hsi-Hsin Shih

Lipen Yuan

The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

Methods for integrated circuit design and fabrication

An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Integrated circuit and method of manufacturing same

A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.

Semiconductor device including source/drain contact having height below gate stack

A method (of manufacturing conductors for a semiconductor device) includes: forming active regions (ARs) in a first layer, the ARs extending in a first direction; forming a conductive layer over the first layer; forming first, second and third caps over the conductive layer, the caps extending in a second direction perpendicular to the first direction, and the caps having corresponding first, second and third sensitivities that are different from each other; removing portions of the conductive layer not under the first, second or third caps resulting in gate electrodes under the first caps and first and second drain/source (D/S) electrodes correspondingly under the second or third caps; and selectively removing portions of corresponding ones of the first D/S electrodes and the second D/S electrodes.

Method of manufacturing conductors for semiconductor device

In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

Method of manufacturing semiconductor devices

In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.

An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Buried metal track and methods forming same

A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

Landing metal etch process for improved overlay control

The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Metal rail conductors for non-planar semiconductor devices

A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

Buried metal for FinFET device and method

Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Line-end extension method and device

A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

Self aligned litho etch process patterning method

An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.

Contact structure, method, layout, and system

An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

Via connection to a partially filled trench

The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Method for routing local interconnect structure at same level as reference metal line

Growing community of inventors

Hsinchu, Taiwan

Chih-Ming Lai